Abstract: Methods, kits, and compositions are provided herein that can be used to treat hematopoietic disorders using an anti-CD47 agent such as an antibody and a hypomethylating agent, such as azacitidine.

Abstract: A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.

Abstract: A system and method for performance modeling of integrated circuits is provided. A method for performing timing analysis on an integrated circuit is provided, the integrated circuit having a timing path. The method includes computing a number of non-common timing path elements in the timing path, assigning a timing de-rate factor to the timing path based on the number of non-common timing path elements, and computing a timing analysis on the integrated circuit using the assigned timing de-rate factor.

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract: A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.

Abstract: A system and method for performance modeling of integrated circuits is provided. A method for performing timing analysis on an integrated circuit is provided, the integrated circuit having a timing path. The method includes computing a number of non-common timing path elements in the timing path, assigning a timing de-rate factor to the timing path based on the number of non-common timing path elements, and computing a timing analysis on the integrated circuit using the assigned timing de-rate factor.

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract: A method and system of improving signal integrity in integrated circuit designs is disclosed. In some embodiments, signal integrity optimization is conducted in conjunction with detailed routing of an integrated circuit design based upon a global routing plan previously generated for the design.

Abstract: A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.

Abstract: A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.

Abstract: A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment the driver is formed in a micro cell. A signal line is connected to the pin and the driver.