Patents by Inventor Louis De La Cruz
Louis De La Cruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7859919Abstract: The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.Type: GrantFiled: August 27, 2008Date of Patent: December 28, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Louis A. De La Cruz, II, Scott I. Remington
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Patent number: 7685483Abstract: Systems and methods are disclosed herein to provide test features for integrated circuits. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an input signal path adapted to route an address signal for a configurable memory. An input multiplexer, coupled to the input signal path, is controllable to route a first test signal provided via the input signal path for at least one memory configuration that does not use the input signal path for the address signal.Type: GrantFiled: June 20, 2005Date of Patent: March 23, 2010Assignee: Lattice Semiconductor CorporationInventors: Allen White, Hemanshu T. Vernenker, Louis De La Cruz
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Publication number: 20100054051Abstract: The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.Type: ApplicationFiled: August 27, 2008Publication date: March 4, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Louis A. De La Cruz, II, Scott I. Remington
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Patent number: 7378879Abstract: Systems and methods are disclosed herein for decoder applications. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a decoder that receives a plurality of input signals and partially decodes the input signals based on their true and complement values to provide a plurality of decoded signals. The decoded signals, for example, may be utilized to control a multiplexer.Type: GrantFiled: June 20, 2005Date of Patent: May 27, 2008Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Hemanshu T. Vernenker
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Patent number: 7342846Abstract: Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.Type: GrantFiled: July 22, 2005Date of Patent: March 11, 2008Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Allen R. White, Hemanshu T. Vernenker
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Patent number: 7317343Abstract: In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.Type: GrantFiled: October 25, 2005Date of Patent: January 8, 2008Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Hemanshu T. Vernenker
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Patent number: 7221607Abstract: Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at least one column of memory having a plurality of memory cells and at least two ports and a dummy column having a dummy memory cell and a first port and a second port. At least one bit line is provided for each port of the columns of memory and the dummy column, with the dummy column adapted to provide a read timing indication by performing a write operation through the first port at substantially the same time as a read operation through the second port.Type: GrantFiled: February 9, 2005Date of Patent: May 22, 2007Assignee: Lattice Semiconductor CorporationInventors: Hemanshu T. Vernenker, Louis De La Cruz, Allen White
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Publication number: 20070019495Abstract: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.Type: ApplicationFiled: July 22, 2005Publication date: January 25, 2007Inventors: Louis De La Cruz, Allen White, Hemanshu Vernenker
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Patent number: 7102934Abstract: Systems and methods including sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier for a memory array having an associated precharge circuit and a read completion detection circuit.Type: GrantFiled: May 17, 2006Date of Patent: September 5, 2006Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Allen White
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Patent number: 7068556Abstract: Systems and methods to provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier is disclosed having an associated precharge circuit and a read completion detection circuit.Type: GrantFiled: March 9, 2004Date of Patent: June 27, 2006Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Allen White
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Patent number: 6998896Abstract: Systems and methods provide metastability-resistant techniques. For example, in accordance with an embodiment of the present invention, a flip flop is disclosed having a dynamic gain skewed to provide metastability resistance.Type: GrantFiled: April 21, 2004Date of Patent: February 14, 2006Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Christopher Hume, Allen White
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Patent number: 6639449Abstract: A clock multiplexer selects between two asynchronous clock signal inputs to produce a clock signal output such that the clock signal input corresponding to the clock signal output may be denoted as the current clock signal and the remaining clock signal input may be denoted as the selected clock signal. After detecting an edge of a specified type in the current clock signal, the clock multiplexer holds the clock signal output either high or low according to the specified type of clock edge being detected. After detecting an edge of the specified type in the selected clock signal, the clock signal output is released and the selected clock signal allowed to pass.Type: GrantFiled: October 22, 2002Date of Patent: October 28, 2003Assignee: Lattice Semiconductor CorporationInventors: Louis De La Cruz, Chris Hume