Abstract: A method of sending data packets between a control processor and a plurality of peripheral components comprising retrieving information embedded in a command data packet formatted in a first protocol at a switch adapted to function as an alternate bus, forming a reformatted data packet at the switch, and transferring the reformatted data packet from the switch. The reformatted data packet is formatted according to a second protocol, and includes the retrieved information.

Abstract: A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method including embedding a component address having a length of up to seven bits in a System Management Bus Block Write and completing a system transaction with the System Management Bus Block Write and a second data packet so that data is sent between the control processor and the peripheral component having the component address.

Abstract: In a communications environment wherein data terminal equipment (DTE) transmits a data signal to data communication equipment (DCE) synchronously with a clocking signal provided by the DCE to the DTE, a circuit and method are configured to automatically detect a condition in which the data signal is sampled near a transition in the data signal, which may result in system clocking errors. Upon detecting this condition, the clocking signal used to sample the data signal is automatically inverted relative to the data signal to ensure that that the data signal is sampled near the midpoint between transitions in the data signal. In this manner, data clocking errors may be significantly reduced.

Abstract: The present invention is a hardware implementation of frame relay switching functions which provides for real time concurrent multiple processes by implementing the processes in dedicated hardware logic operating in parallel, whereas in a typical software implementation the processes are sequentially processed. While data structures in software based implementations are accessed on some multiple of a byte regardless of the logical structure of the data, in the hardware implementation of the present invention the physical widths and the logical widths of the data structure elements are identical. This allows direct access of the logical structure by the operating process.