Patents by Inventor Louis Feng

Louis Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210297801
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Application
    Filed: December 28, 2020
    Publication date: September 23, 2021
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Patent number: 11120766
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
  • Patent number: 11062506
    Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Patent number: 11049214
    Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
  • Patent number: 10964091
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Chandrasekaran Sakthivel, Michael Apodaca, Kai Xiao, Altug Koker, Jeffery S. Boles, Adam T. Lake, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, James M. Holland, Prasoonkumar Surti, Jonathan Kennedy, Louis Feng, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Patent number: 10922227
    Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M Cimini, Abhishek R. Appu
  • Publication number: 20210020143
    Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
    Type: Application
    Filed: May 28, 2020
    Publication date: January 21, 2021
    Applicant: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
  • Patent number: 10896657
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
  • Patent number: 10880666
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Publication number: 20200402298
    Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Patent number: 10853995
    Abstract: Systems, apparatuses and methods may provide for technology that computes, by a shader in a fixed-functionality hardware shader library, a physically based shading model for a type of material. Additionally, the shader may shade one or more surfaces associated with the type of material in accordance with the physically based shading model. In one example, two or more shaders in the shader library are dedicated to different types of materials.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
  • Patent number: 10783603
    Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler
  • Patent number: 10706612
    Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Publication number: 20200211150
    Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
  • Patent number: 10672366
    Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
  • Publication number: 20200051524
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 16, 2019
    Publication date: February 13, 2020
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
  • Patent number: 10546411
    Abstract: Embodiments provide for an apparatus including one or more processors having logic to enumerate a directed path through nodes of a directed acyclic graph, the logic to determine a key for a node and a path identifier for a directed path between nodes of the directed acyclic graph.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 28, 2020
    Assignee: INTEL CORPORATION
    Inventor: Louis Feng
  • Publication number: 20200005526
    Abstract: Systems, apparatuses and methods may provide for technology that computes, by a shader in a fixed-functionality hardware shader library, a physically based shading model for a type of material. Additionally, the shader may shade one or more surfaces associated with the type of material in accordance with the physically based shading model. In one example, two or more shaders in the shader library are dedicated to different types of materials.
    Type: Application
    Filed: June 12, 2019
    Publication date: January 2, 2020
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
  • Publication number: 20200005734
    Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
  • Patent number: 10521876
    Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini