Patents by Inventor Louis Galbiati, III

Louis Galbiati, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
    Patent number: 5452239
    Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: September 19, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Wei-Jin Dai, Louis Galbiati, III, Joseph Varghese, Dam V. Bui, Stephen P. Sample