Patents by Inventor Louis H. Odenwald, Jr.

Louis H. Odenwald, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7849248
    Abstract: At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: December 7, 2010
    Assignee: LSI Corporation
    Inventors: Stephen B. Johnson, Timothy E. Hoglund, Louis H. Odenwald, Jr.
  • Publication number: 20100064085
    Abstract: At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.
    Type: Application
    Filed: April 2, 2009
    Publication date: March 11, 2010
    Inventors: Stephen B. Johnson, Timothy E. Hoglund, Louis H. Odenwald, JR.
  • Patent number: 7228361
    Abstract: A system and method are described for increasing performance of operations implemented in a storage system utilizing fibre channel, such as by enabling full duplex opens when a JBOD/bridge is involved. In an aspect of the present invention, a method of performing a full duplex open in a fibre channel network having an initiator and a bridge may include initiating an open by the initiator with the bridge. The bridge has a primary physical address and an alias physical address. The alias physical address represents a target device communicatively coupled to the bridge, wherein the open is initiated utilizing the primary physical address. The initiator communicates with the target device.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 5, 2007
    Assignee: LSI Logic Corporation
    Inventors: Louis H. Odenwald, Jr., Steve R. Schremmer
  • Patent number: 7080197
    Abstract: The present invention is directed to a system and method of cache management for storage controllers. In an aspect of the present invention, a system for storing electronic data may include a host and a data storage apparatus communicatively coupled to the host. The host has cache coherency functionality. The data storage apparatus includes a first storage controller communicatively coupled to at least one storage device, the first storage controller further coupled to a first cache. A second storage controller is also included, which is communicatively coupled to at least one storage device, the second storage controller further coupled to a second cache. The cache coherency functionality of the host provides coherency of the first cache coupled to the first storage controller with the second cache coupled to the second storage controller.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventor: Louis H. Odenwald, Jr.
  • Patent number: 6721320
    Abstract: The invention relates to an improved Fiber Channel data management technique. More specifically, this patent relates to an improved scheme for managing the related data in related frames that form a sequence. This patent also generally relates to the management of multiple, active sequences which are simultaneously in transit on a Fiber Channel. This invention provides a means for efficiently locating the sequence status block associated with an arbitrary Fiber Channel sequence by using the source identifier field, the originator exchange identifier field and/or the sequence identifier fields of a Fiber Channel frame header to construct a hash table lookup search.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Timothy E. Hoglund, Louis H. Odenwald, Jr., Elizabeth G. Rodriguez
  • Patent number: 6310884
    Abstract: A method of using a frame sequence to transmit a data block from a transmitting device to a receiving device is disclosed. One step of the method includes generating a first frame of the frame sequence that includes a last portion of the data block and a relative offset which indicates a relative displacement between a first portion of the data block and the last portion of the data block. Another step of the method includes generating a second frame of the frame sequence that includes the first portion of the data block. The method also includes the step of transmitting the first frame of the frame sequence from the transmitting device to the receiving device before transmitting the second frame. Yet another step of the method includes receiving the first frame of the frame sequence from the transmitting device before receiving the second frame.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: October 30, 2001
    Assignee: LSI Logic Corporation
    Inventor: Louis H. Odenwald, Jr.
  • Patent number: 6065085
    Abstract: The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primary bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: May 16, 2000
    Assignee: LSI Logic Corporation
    Inventors: Louis H. Odenwald, Jr., Steven R. Schremmer