Abstract: A method, in a computer system having a centralized spin lock controller arrangement, for managing a spin lock between a first processor and a second processor. The first processor holds the spin lock, the second processor contends for the spin lock, and the spin lock is implemented using a line of memory. The method includes invalidating a first private copy of the line that is held by the first processor. The method further includes providing a second private copy of the line to the second processor even before the first processor releases the spin lock, thereby preventing the second processor from requesting for a private copy of the line again while the spin lock is still held by the first processor.

Abstract: In an embodiment of the invention, a method for providing cooperating triggers, includes: determining if a match criteria for a slave trigger and a match criteria for a primary trigger are met; executing the slave trigger and the primary trigger if the match criteria are met; and waiting for a transition in a total number of shots taken by the primary trigger so that the slave trigger performs synchronization spinning. The primary trigger and the slave trigger can then perform post synchronization spinning.

Abstract: In an embodiment of the invention, an apparatus for device switch error injection, includes: an operating system kernel including a device driver and a device switch error driver. The device switch error driver intercepts a system call to the device driver to simulate a system call error. In another embodiment of the invention, a method for device switch error injection includes: receiving a system call from an application; and intercepting, by a device switch error driver, the system call to simulate a system call error.

Abstract: In an embodiment of the invention, an apparatus for generating a maximum change data pattern, includes: a shift stage configured to shift a generated signal to the right by one bit and to generate a shifted signal; a logic stage configured to perform an XOR function on the signal and the shifted signal, and generate an XOR output signal; a complement stage configured to complement the XOR output signal, and to generate a complement stage output signal; and a selector configured to select the XOR output signal if the generated signal is even and to select the complement stage output signal if the generated signal is odd.

Abstract: In an embodiment of the invention, a method for a phase adjusted delay loop, includes: determining a requested delay value for a code path; and executing a delay loop in the code path in order to obtain a loop delay value that is in phase with the requested delay value. The act of executing the delay loop may include: executing at least one No-operation instruction (NOP) to adjust the loop delay value and to adjust the phase of the loop delay value.