Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: An input protection circuit for a MOS device uses back-to-back zener diodes 30 and 40 with the anodes 130 and 150 connected and floating. This circuitry protects against positive and negative ESD events and does not interfere with the normal operation of the MOS device. The inventive circuit allows an improved gate operating range of the forward bias voltage of a first diode 30 plus the breakdown voltage of a second diode 40 below the supply voltage to the breakdown voltage of the first diode 30 plus the forward bias voltage of the second diode 40 above the supply voltage.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (139/140); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (141, 142) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (143); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (144, 145); vertical and lateral annular DMOS transistors (146, 147); a Schottky diode (148); and a FAMOS EPROM cell (149). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A field effect transistor (147) is formed in a region of a second semiconductor layer (171), having a first conductivity type. A tank region (196) of a second conductivity type opposite the first conductivity type is formed in the semiconductor region (171), and defines a tank area on the face of the semiconductor layer (171). A first highly doped region (276) formed to be of the first conductivity type is formed within the region (171) and to be spaced from the tank region (196). A gate insulator layer (218) is formed on at least one selected portion of the face, this selected portion including a portion of the tank area (196). A conductive gate (246) is formed on the gate insulator layer over the selected portion of the face. At least one second highly doped region (278) is formed at the face within the tank area to be of the first conductivity type, and to have at least one lateral edge self-aligned to a corresponding one of the lateral edges of the gate (246 ).