Abstract: A technique is disclosed for distinguishing parasitic cell failures from other type failures of cells in a memory array. A parasitic failure is defined as one action between cells "k" and "j" such that writing into cell "j" causes a change in cell "k" without intentionally writing into cell "k."A binary pattern generator, produces array test patterns equivalent to a Hamming single error correction code. Each of the patterns is associated with a syndrome bit position and is used to test each array address in turn. Each pattern is read back out by array address and the results are stored in a separate memory for storing the failing syndromes for each failing cell array address. For each cell failure, the syndrome bits form an "address" which is exclusive ORed with the address of the failed cell to yield the address of the root cell causing coupling (parasitic) failure of the failed cell.

Abstract: A system for providing test data for testing a semiconductor memory includes generation means for successively developing generated data patterns beginning from a seed data pattern, such that every distinct data pattern of the seed data pattern is successively developed in a forward sequence and, subsequently, the distinct data patterns are successively developed in a reverse sequence relative to the forward sequence.

Abstract: A high speed tester stores the data corresponding to the first and last addresses of each test loop in a high speed cache. In the majority of test addresses, data is transferred from a memory into at least two shift registers and the cache is not accessed. The output of the shift registers are interleaved in a multiplexer to provide two bits of test data for each tester clock cycle. Control circuitry decodes bits associated with each data address and controls presenting data to the shift registers from the memory and the cache. Use of the cache allows a continuous output of test data from the multiplexer during repetitions of a loop and when new test loop are introduced, with no intervals in the data, regardless of whether the data terminates on an address boundary.

Abstract: A tester of circuit devices is disclosed which uses commercially available component parts but is capable of high performance testing of hierarchical memory cards requiring data pulses of variable pulse widths at high repetition rates. The tester includes two memories connected to respective shift registers which in turn, feed a multiplexer. The memories handle test timing patterns for respective halves of the basic clock test cycle and are interleaved in operation along with the shift registers. Two opposite-phased outputs of the multiplexer are applied through respective programmable delay networks and pulse generators to the set and reset inputs of a trigger circuit. The trigger circuit provides test data to a dedicated input pin of the device under test.

Abstract: A multi-layered package for a magnetic domain device including self-contained in-plane switching magnetic field coils surrounding one or more magnetic domain device chips and a permanent magnet surrounding the switching magnetic field coils. The switching coils are formed by two printed circuit layers, each layer comprising an insulating substrate having striped conductive patterns orthogonally oriented relative to each other on the opposite surfaces of the insulating layer. The ends of the striped conductors on one printed circuit layer are connected to the ends of the corresponding striped pattern on the other printed circuit layer so as to form one of the switching coils. The ends of the other pair of striped conductive patterns are similarly connected to form the second switching coil. The magnetic domain device chips are placed inside the formed switching coils which, in turn, are surrounded by the permanent magnet.