Abstract: An apparatus has processing circuitry and a memory system. The memory system is responsive to a first type of memory access operation for which a time taken to handle the memory access operation is unbounded, the operation is able to change contents of data stored in the memory system, and a response is required. The apparatus has memory access operation handling circuitry that receives an indication of an interrupt to be taken while a memory access operation of the first type is being handled by the memory system and determines whether the memory access operation has reached a stage for which a remaining time to complete the memory access operation will be bounded. In dependence on the remaining time, the memory access operation handling circuitry either stalls the interrupt until the memory access operation has completed or aborts the memory access operation and allow the interrupt to be taken.