Patents by Inventor Louis L. C. Hsu
Louis L. C. Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8687445Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: March 18, 2013Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Patent number: 8422322Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: November 3, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Publication number: 20120051166Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: ApplicationFiled: November 3, 2011Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Patent number: 8098536Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: January 24, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Patent number: 8023305Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.Type: GrantFiled: June 10, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. C. Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang
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Patent number: 8009453Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.Type: GrantFiled: June 10, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. C. Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang
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Patent number: 7983069Abstract: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.Type: GrantFiled: June 25, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Brian L. Ji, Chung Hon Lam
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Patent number: 7838873Abstract: A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.Type: GrantFiled: August 18, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Matthew E. Colburn, Timothy J. Dalton, Michael C. Gaidis, Louis L. C. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7825420Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.Type: GrantFiled: August 12, 2009Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Carl Radens, Lawrence A. Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7749778Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.Type: GrantFiled: January 3, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Lawrence Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Chih-Chao Yang
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Patent number: 7635884Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.Type: GrantFiled: July 29, 2005Date of Patent: December 22, 2009Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Carl Radens, Lawrence A. Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20090302405Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.Type: ApplicationFiled: August 12, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael C. Gaidis, Carl Radens, Lawrence A. Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20090190413Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Patent number: 7560310Abstract: A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.Type: GrantFiled: December 27, 2007Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Jack Allan Mandelman
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Patent number: 7544578Abstract: A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.Type: GrantFiled: January 3, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Matthew E. Colburn, Timothy J. Dalton, Michael C. Gaidis, Louis L. C. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7514271Abstract: A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.Type: GrantFiled: March 30, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. C. Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang
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Publication number: 20080308801Abstract: A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.Type: ApplicationFiled: August 18, 2008Publication date: December 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Matthew E. Colburn, Timothy J. Dalton, Michael C. Gaidis, Louis L. C. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7460389Abstract: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.Type: GrantFiled: July 29, 2005Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Brian L. Ji, Chung Hon Lam
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Publication number: 20080253177Abstract: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.Type: ApplicationFiled: June 25, 2008Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: Louis L.C. Hsu, Brian L. Ji, Chung Hon Lam
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Publication number: 20080239785Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.Type: ApplicationFiled: June 10, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L.C. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang