Patents by Inventor Louis Lim
Louis Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130034954Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: October 8, 2012Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Publication number: 20100013003Abstract: An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu CHEN, Donghua LIU, Sung Mun JUNG, Swee Tuck WOO, Rachel LOW, Louis LIM, Siow Lee CHWA
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Patent number: 7595237Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: GrantFiled: April 27, 2007Date of Patent: September 29, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Patent number: 7585746Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.Type: GrantFiled: July 12, 2006Date of Patent: September 8, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
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Publication number: 20080266944Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Publication number: 20080032513Abstract: An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: July 5, 2006Publication date: February 7, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Publication number: 20080014707Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.Type: ApplicationFiled: July 12, 2006Publication date: January 17, 2008Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
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Publication number: 20060088897Abstract: Disclosed is an isoform-specific antagonist of PAK kinase, which is preferably a molecule capable of modulating an interaction between Nck and a PAK isoform. In particular, ?PAK, ?PAK and ?PAK specific inhibitors are disclosed. Also included are methods of treating diseases, preferably characterised by a defect in nerve regeneration, comprising modulating an activity of a PAK kinase isoform, preferably ?PAK kinase or ?PAK kinase, or both.Type: ApplicationFiled: September 21, 2005Publication date: April 27, 2006Inventors: Louis Lim, Sohail Ahmed, Robert Kozma
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Patent number: 7029976Abstract: A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge storing layer (ONO) from various etches used in the process to pattern the various gate dielectric layers on other regions of substrate.Type: GrantFiled: January 21, 2005Date of Patent: April 18, 2006Assignee: Chartered Semiconductor Manufacturing. LTDInventors: Sripad Sheshagiri Nagarad, Dong Kyun Sohn, Yoke Leng Louis Lim, Siow Lee Chwa, Hsiang Fang Lim