Abstract: A sample-and-hold circuit includes a transconductance cell and an inductive-capacitive (L-C) resonator circuit acting as a bandpass filter.

Abstract: The use of a dynamic current bias technique to dynamically bias a voltage switch of a sample-and-hold circuit is disclosed. Dynamically biasing the voltage switch mitigates nonlinear distortion caused by VBE (VGS) variation during charging and discharging the holding capacitor of the sample-and-hold circuit The bandwidth of the sample-and-hold circuit is enhanced.

Abstract: A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.

Abstract: A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance R3 and a first resistance R1 disposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance R1 is disposed in series with the first inductor and is equal to the parasitic resistance RL1 thereof. Likewise, a second resistance R2 is disposed in series with the second inductor and is equal to the parasitic resistance RL2 thereof. The Q enhancement circuit further includes a first transistor Q1 and a second transistor Q2.

Abstract: A mismatch shaped analog to digital converter. The novel analog to digital converter includes a first circuit for providing a plurality of reference voltages, a plurality of comparators adapted to compare an input signal with the reference voltages, and a second circuit for randomizing connections between the reference voltages and the comparators. The connections are randomized such that noise caused by mismatch errors is spectrally shaped according to a desired noise-shaping characteristic. In an illustrative embodiment, the second circuit includes a noise-shaping circuit comprised of a plurality of Delta-Sigma modulators for generating one or more control signals, and a router for connecting the reference voltages to the comparators in accordance with the control signals. The mismatch shaped analog to digital converter can be used within a Delta-Sigma modulator to shape noise caused by mismatch errors in the feedback digital to analog converter.

Abstract: A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.

Abstract: A mismatch shaped analog to digital converter. The novel analog to digital converter includes a first circuit for providing a plurality of reference voltages, a plurality of comparators adapted to compare an input signal with the reference voltages, and a second circuit for randomizing connections between the reference voltages and the comparators. The connections are randomized such that noise caused by mismatch errors is spectrally shaped according to a desired noise-shaping characteristic. In an illustrative embodiment, the second circuit includes a noise-shaping circuit comprised of a plurality of Delta-Sigma modulators for generating one or more control signals, and a router for connecting the reference voltages to the comparators in accordance with the control signals. The mismatch shaped analog to digital converter can be used within a Delta-Sigma modulator to shape noise caused by mismatch errors in the feedback digital to analog converter.

Abstract: The use of a dynamic current bias technique to dynamically bias a voltage switch of a sample-and-hold circuit is disclosed. Dynamically biasing the voltage switch mitigates nonlinear distortion caused by VBE (VGS) variation during charging and discharging the holding capacitor of the sample-and-hold circuit The bandwidth of the sample-and-hold circuit is enhanced.

Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.

Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.

Abstract: A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance R3 and a first resistance R1 disposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance R1 is disposed in series with the first inductor and is equal to the parasitic resistance RL1 thereof. Likewise, a second resistance R2 is disposed in series with the second inductor and is equal to the parasitic resistance RL2 thereof. The Q enhancement circuit further includes a first transistor Q1 and a second transistor Q2.