Patents by Inventor Louis-Marie Vincent Mouton
Louis-Marie Vincent Mouton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9361112Abstract: A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed.Type: GrantFiled: April 18, 2013Date of Patent: June 7, 2016Assignee: ARM LimitedInventors: Clément Marc Demongeot, Louis-Marie Vincent Mouton, Frédéric Claude Marie Piry, Jocelyn Francois Orion Jaubert, Albin Pierick Tonnerre
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Patent number: 9323536Abstract: A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack.Type: GrantFiled: May 2, 2013Date of Patent: April 26, 2016Assignee: ARM LimitedInventors: Clement Marc Demongeot, Louis-Marie Vincent Mouton, Jocelyn Francois Orion Jaubert
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Patent number: 9311088Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.Type: GrantFiled: June 26, 2013Date of Patent: April 12, 2016Assignee: ARM LimitedInventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Luca Scalabrino, Richard Roy Grisenthwaite, David Hennah Mansell
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Publication number: 20140164742Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.Type: ApplicationFiled: June 26, 2013Publication date: June 12, 2014Inventors: Frederic Claude Marie PIRY, Louis-Marie Vincent MOUTON, Luca SCALABRINO, Richard Roy GRISENTHWAITE, David Hennah MANSELL
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Patent number: 8706965Abstract: An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry.Type: GrantFiled: June 3, 2011Date of Patent: April 22, 2014Assignee: ARM LimitedInventors: Frederic Claude Piry, Louis-Marie Vincent Mouton, Luca Scalabrino
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Patent number: 8578136Abstract: An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry.Type: GrantFiled: June 15, 2010Date of Patent: November 5, 2013Assignee: ARM LimitedInventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Luca Scalabrino, Richard Roy Grisenthwaite, David Hennah Mansell
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Patent number: 8151055Abstract: A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.Type: GrantFiled: February 25, 2009Date of Patent: April 3, 2012Assignee: ARM LimitedInventors: Louis-Marie Vincent Mouton, Nicolas Jean Phillippe Huot, Gilles Eric Grandou, Stephane Eric Sebastian Brochier
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Publication number: 20110314224Abstract: An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry.Type: ApplicationFiled: June 3, 2011Publication date: December 22, 2011Applicant: ARM LimitedInventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Luca Scalabrino
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Publication number: 20110307681Abstract: An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry.Type: ApplicationFiled: June 15, 2010Publication date: December 15, 2011Inventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Luca Scalabrino, Richard Roy Grisenthwaite, David Hennah Mansell
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Patent number: 7925871Abstract: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.Type: GrantFiled: February 19, 2008Date of Patent: April 12, 2011Assignee: ARM LimitedInventors: Louis Marie Vincent Mouton, Nicolas Huot, Stephane Eric Sebastien Brochier, Gilles Eric Grandou
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Patent number: 7783869Abstract: A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instrType: GrantFiled: December 19, 2006Date of Patent: August 24, 2010Assignee: ARM LimitedInventors: Gilles Eric Grandou, Stephane Eric Sebastien Brochier, Louis-Marie Vincent Mouton
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Patent number: 7596663Abstract: A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one ofType: GrantFiled: November 15, 2006Date of Patent: September 29, 2009Assignee: ARM LimitedInventors: Louis-Marie Vincent Mouton, Gilles Eric Grandou, Stephane Eric Brochier
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Publication number: 20090235029Abstract: A data processing apparatus is disclosed that comprises: at least one data processor for processing data; a set associative cache for storing a plurality of values to be processed by said data processor, each value being identified by an address of a memory location within a memory storing said value, said set associative cache being divided into a plurality of cache ways; a data store comprising a plurality of storage locations for storing a plurality of identifiers, each identifier identifying a cache way that a corresponding value from said set associative cache is stored in and each having a valid indicator associated therewith, said plurality of identifiers corresponding to a plurality of values, said plurality of values being values stored in consecutive addresses such that said data store stores identifiers for values stored in a region of said memory; current pointer store for storing a current pointer pointing to a most recently accessed storage location in said data store; offset determining circuitType: ApplicationFiled: February 25, 2009Publication date: September 17, 2009Applicant: ARM LIMITEDInventors: Louis-Marie Vincent Mouton, Nicolas Jean Phillippe Huot, Gilles Eric Grandou, Stephane Eric Sebastian Brochier
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Publication number: 20090210685Abstract: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Applicant: ARM LimitedInventors: Louis-Marie Vincent Mouton, Nicolas Huot, Stephane Eric Sebastien Brochier, Gilles Eric Grandou
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Patent number: 7571305Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.Type: GrantFiled: January 11, 2007Date of Patent: August 4, 2009Assignee: ARM LimitedInventors: Fredrick Claude Marie Piry, Louis-Marie Vincent Mouton, Stephane Eric Sabastien Brochier, Gilles Eric Grandou
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Publication number: 20080172547Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: ARM LimitedInventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Stephane Eric Sabastien Brochier, Gilles Eric Grandou
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Publication number: 20080148028Abstract: A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instrType: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Gilles Eric Grandou, Stephane Eric Sebastien Brochier, Louis-Marie Vincent Mouton
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Publication number: 20080114939Abstract: A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one ofType: ApplicationFiled: November 15, 2006Publication date: May 15, 2008Applicant: ARM LimitedInventors: Louis-Marie Vincent Mouton, Gilles Eric Grandou, Stephane Eric Sebastien Brochier