Abstract: Logic circuitry is provided for controlling the transfer of data between 1) a low cost pipelined processor and its associated memory, 2) between the processor and input/output devices, and 3) between the input/output devices and memory. A plurality of unidirectional busses are provided to interface the processor and memory and a bidirectional buss is provided to interface with the input/output devices. The logic circuitry provides a control function to steer data over the proper buss structures interconnecting the processor, the memory and the input/output devices and provides those interconnections in a manner which allows the processor to overlap input and output functions.

Abstract: A method of both testing all loops of a long serial magnetic bubble domain chip, and repairing the chip for automatic bypass of defective loops. Each repair station associated with each loop is sequentially loaded with a bubble domain. Then new domains are sequentially generated and positioned adjacent each loop. The domains initially loaded into the repair stations are shifted out in parallel for propagation along the loops. The new domains are then loaded in parallel into the repair stations. The domains propagated along the loops are read to determine defective loops, and form a basis for generating a repair pattern. The repair pattern is then loaded in parallel into the repair stations for sealing off defective loops.