Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.

Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.

Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.

Abstract: A capacitance-to-digital converter circuit utilizes a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.

Abstract: A capacitance-to-digital converter circuit s a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.

Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.

Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.

Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.

Abstract: A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level.

Abstract: A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level.

Abstract: Equalization techniques in clock recovery receivers may include use of a passive equalizer prior to amplification, combined frequency paths in and active and/or passive equalizer, capacitive degeneration and/or negative feedback with low-pass filtering in an active equalizer, a decision feedback equalizer with multiple decision paths, and programmable tail currents to change switching points. A compensation circuit for a pre/post equalizer may include an oscillator fabricated from replica components to compensate for process variations and a look-up table to provide process variation correction in response to programmed equalizer settings.

Abstract: A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage. The switching circuit has an inherent temperature profile associated therewith. A voltage divider circuit outputs a defined trip voltage that is compensated over the temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for the free running clock circuit. The voltage divider circuit has a top programmable resistor array connected in series with at least two programmable resistor arrays between two supply terminals of differing voltages.

Abstract: A Hebbian synapse emulation circuit models the conductance of a synapse circuit. In one embodiment, the circuit includes a counter that provides control signals determining the conduction states of electrical pathways, which define the conductance level of the synapse. The counter can increment, decrement, or leave the same, the synapse conductance value based upon potentiation and depression signals that are derived from a voltage that corresponds to the calcium concentration in the synapse. The counter can be coupled to a plurality of synapse circuits on a time-shared basis.

Abstract: A Hebbian synapse emulation circuit models the conductance of a synapse circuit. In one embodiment, the circuit includes a counter that provides control signals determining the conduction states of electrical pathways, which define the conductance level of the synapse. The counter can increment, decrement, or leave the same, the synapse conductance value based upon potentiation and depression signals that are derived from a voltage that corresponds to the calcium concentration in the synapse. The counter can be coupled to a plurality of synapse circuits on a time-shared basis.