Abstract: A computer system includes a first core including a first local cache and a second core including a second local cache. The first core and the second core are coupled through a remote link. A shared cache coupled to the first core and to the second core. The shared cache includes an ownership table that includes a plurality of entries indicating if a cache line is stored solely in the first local cache or solely in the second local cache. The remote link includes a first link between the first core and the shared cache and a second link between the second core and the shared cache.

Abstract: A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

Abstract: A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

Abstract: The disclosed structures and methods are directed to decoders and to methods for decoding codes, for example, polar codes. The decoder comprises: a codeword node decoding pipeline having three logic units, and configured to, for each encoded codeword node: based on a received instruction sequence, adjust the three logic units for decoding of each encoded codeword node, and decode a set of logarithmic likelihood ratios (LLRs) corresponding to the encoded codeword node to generate decoded bits. The decoder also has an output storage configured to store the decoded bits corresponding to each encoded codeword node, and generate a decoded codeword based on the decoded bits. The decoding method comprises adjusting the codeword node decoding pipeline to each encoded codeword node based on codeword node length and a codeword node type, as well as a bit index of the encoded codeword node.

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated with each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract: The disclosed structures and methods are directed to decoders and to methods for decoding codes, for example, polar codes. The decoder comprises: a codeword node decoding pipeline having three logic units, and configured to, for each encoded codeword node: based on a received instruction sequence, adjust the three logic units for decoding of each encoded codeword node, and decode a set of logarithmic likelihood ratios (LLRs) corresponding to the encoded codeword node to generate decoded bits. The decoder also has an output storage configured to store the decoded bits corresponding to each encoded codeword node, and generate a decoded codeword based on the decoded bits. The decoding method comprises adjusting the codeword node decoding pipeline to each encoded codeword node based on codeword node length and a codeword node type, as well as a bit index of the encoded codeword node.

Abstract: The disclosed structures and methods are directed to polar code decoders and methods for polar code decoding. A polar code decoder comprises an input logarithmic likelihood ratio (LLR) distributor, a master polar decoder module (PDM), at least one slave PDM, an intermediate LLR result combiner, and a decoded bit aggregator configured to generate a decoded codeword bit sequence. For each codeword node, each PDM partially decodes one or more sets of LLR subsets, which are sent to the intermediate LLR result combiner to generate an intermediate LLR result sequence. A first node decoding pipeline of the master PDM is configured to decode an intermediate LLR result sequence to generate at least one decoded node bit sequence. A polar code decoder with slave PDMs each having a second node decoding pipeline is also disclosed. A method for polar code decoding is also disclosed.

Abstract: A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker circuit having a plurality of credit units associated with corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, and a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for a given period of time after the positive determination.

Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

Abstract: Coding sub-channel selection involves, in an embodiment, determining, from sub-channels that are defined by a code and that have associated reliabilities for input bits at input bit positions, a first number of the sub-channels to carry bits that are to be encoded. A second number of the sub-channels, greater than the first number, are selected. The second number of sub-channels are selected to provide exactly the first number sub-channels to be available to carry the bits that are to be encoded.

Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

Abstract: Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.

Abstract: Coding sub-channel selection involves, in an embodiment, determining, from sub-channels that are defined by a code and that have associated reliabilities for input bits at input bit positions, a first number of the sub-channels to carry bits that are to be encoded. A second number of the sub-channels, greater than the first number, are selected. The second number of sub-channels are selected to provide exactly the first number sub-channels to be available to carry the bits that are to be encoded.

Abstract: Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.

Abstract: A system and method for multi-branch switching are provided. A memory has stored therein a program comprising at least one sequence of instructions, the at least one sequence of instructions comprising a plurality of branch instructions, at least one branch of the program reached upon execution of each one of the plurality of branch instructions. The processor is configured for fetching the plurality of branch instructions from the memory, separately buffering each branch of the program associated with each one of the fetched branch instructions, evaluating the fetched branch instructions in parallel, and executing the evaluated branch instructions in parallel.

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated to each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker having a plurality of credit units associated to corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for given period of time after the positive determination.