Patents by Inventor Louis Praamsma
Louis Praamsma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9548701Abstract: A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.Type: GrantFiled: March 2, 2015Date of Patent: January 17, 2017Assignee: NXP B.V.Inventors: Timothy John Ridgers, Louis Praamsma
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Publication number: 20160190992Abstract: A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.Type: ApplicationFiled: March 2, 2015Publication date: June 30, 2016Inventors: Timothy John Ridgers, Louis PRAAMSMA
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Patent number: 9214908Abstract: An amplification circuit (100) comprising a first filter (102) and an LNA (110). The first filter (102) comprising an input (104) for receiving an input signal; a first differential output (106); and a second differential output (108). The first filter (102) has a differential mode of operation for frequencies in its pass-band (706, 806) and a common mode of operation for frequencies outside its pass-band (706, 806), and may be an acoustic wave filter. The LNA (110) comprising a first differential input (112) connected to the first differential output (106) of the first filter (102); a second differential input (114) connected to the second differential output (108) of the first filter (102); and an output (116) for providing an amplified output signal.Type: GrantFiled: July 29, 2014Date of Patent: December 15, 2015Assignee: NXP, B.V.Inventors: Marcel Geurts, Louis Praamsma, Michel Groenewegen, Rainier Breunisse, Freek van Straten, Robert Buytenhuijs
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Publication number: 20150078420Abstract: An amplification circuit (100) comprising a first filter (102) and an LNA (110). The first filter (102) comprising an input (104) for receiving an input signal; a first differential output (106); and a second differential output (108). The first filter (102) has a differential mode of operation for frequencies in its pass-band (706, 806) and a common mode of operation for frequencies outside its pass-band (706, 806), and may be an acoustic wave filter. The LNA (110) comprising a first differential input (112) connected to the first differential output (106) of the first filter (102); a second differential input (114) connected to the second differential output (108) of the first filter (102); and an output (116) for providing an amplified output signal.Type: ApplicationFiled: July 29, 2014Publication date: March 19, 2015Inventors: Marcel Geurts, Louis Praamsma, Michel Groenewegen, Rainier Breunisse, Freek van Straten, Robert Buytenhuijs
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Patent number: 8975924Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.Type: GrantFiled: December 27, 2013Date of Patent: March 10, 2015Assignee: NXP B.V.Inventors: Louis Praamsma, Nikola Ivanisevic
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Publication number: 20140191786Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.Type: ApplicationFiled: December 27, 2013Publication date: July 10, 2014Applicant: NXP B.V.Inventors: Louis Praamsma, Nikola Ivanisevic
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Patent number: 6171912Abstract: The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region (3) is located. The gate region (3) is formed by applying an insulating layer (5) to the semiconductor body and providing this insulating layer with a stepped portion (6) in the thickness direction, whereafter a conductive layer (30) is applied to the surface of the semiconductor body (10), which layer is substantially removed again by etching, so that a part (3A) of the conductive layer (30), which part forms part of the gate region (3) and which lies against the stepped portion (6), remains intact.Type: GrantFiled: November 19, 1998Date of Patent: January 9, 2001Assignee: U.S. Philips CorporationInventor: Louis Praamsma
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Patent number: 5719428Abstract: A semiconductor device with a semiconductor body (3) including a surface region (5) of a first conductivity type which adjoins a surface (4) and in which a field effect transistor (1) with insulated gate (6) is provided. The field effect transistor (1) has source and drain regions (7, 8, respectively) of the second, opposed conductivity type situated in the surface region (5), and a channel region (9) of the first conductivity type situated between the source and drain regions. A metal gate electrode (6) separated from the channel region (9) by an insulating layer (10) is provided over the channel region (9) and is provided with a protection device (2) against excessive voltages applied to the gate electrode (6).Type: GrantFiled: May 24, 1996Date of Patent: February 17, 1998Assignee: U.S. Philips CorporationInventors: Wilhelmus G. Voncken, Louis Praamsma
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Patent number: 5528065Abstract: A dual-gate insulated gate field effect device (1) such as a MOS tetrode has an active device area (3) in which adjacent source regions (5) are separated by and spaced apart from an intervening drain region (6) to define a respective conduction channel region (7) between each source and drain region (5 and 6). An insulated gate structure (10) has first insulated gate sections (11) forming an inner insulated gate (110) connected so as to surround each drain region 6 and second insulated gate sections (12) provided between the first insulated gate sections (11) and the source regions (5) and forming an outer insulated gate (120). Ends (11a,12a) of the insulated gate sections (11 and 12) extend onto the surrounding field oxide (4) to connect with respective first and gate conductors (13 and 14).Type: GrantFiled: June 1, 1995Date of Patent: June 18, 1996Assignee: U.S. Philips CorporationInventors: Stephen J. Battersby, Louis Praamsma
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Patent number: 5216383Abstract: A controllable amplifier circuit includes, successively, in a cascode arrangement between a power supply voltage and ground, a control transistor and a field effect amplifier transistor having a control input for applying a gain control signal thereto and a gate input for applying an input signal thereto, respectively, via which control transistor the field effect amplifier transistor supplies an output signal to a signal output of the controllable amplifier circuit. The control transistor varies the working point of the field effect amplifier transistor in the ohmic range in dependence upon the gain control signal, at least in a part of the control range of the gain control signal. The circuit can be used with a low power supply voltage because the controllable amplifier circuit includes a controllable bias circuit which is coupled to the gate input of the field effect amplifier transistor for applying a controllable bias voltage thereto.Type: GrantFiled: April 23, 1992Date of Patent: June 1, 1993Assignee: U.S. Philips CorporationInventors: Teunis H. Uittenbogaard, Louis Praamsma
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Patent number: 5216269Abstract: Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern.Type: GrantFiled: August 8, 1991Date of Patent: June 1, 1993Assignee: U.S. Philips Corp.Inventors: Jan Middelhoek, Gerrit-Jan Hemink, Rutger C. M. Wijburg, Louis Praamsma, Roger Cuppens