Abstract: A method for preventing radioactive contamination of porous surfaces comprising providing an apparatus for handling radioactive material comprising a porous surface; exposing the porous surface to a vacuum; depositing a flowable precursor material onto the porous surface, wherein the porous surface comprises pores and the vacuum is effective to substantially fill the pores with the flowable precursor material; subjecting the flowable precursor material to energy sufficient to convert the flowable precursor material to an effective sealant film comprising amorphous carbon. In a preferred embodiment, the porous surface is an anodized aluminum surface.

Abstract: Serial communication circuitry (10) having multiple queues (11-14) for use in a data processing system (95). Each queue (11-14) has multiple entries (52). Serial transfers from the multiple queues (11-14) are carried out under the control of global parameters (e.g. 205, 209), per-queue parameters (e.g. 211-212, 214-217), and per-entry parameters (e.g. 350-361). Each queue can be programmed to have a different set of per-queue parameters, and each entry within a queue can be programmed to have a different set of per-entry parameters. In addition, serial communication circuitry (10) can perform serial data transfers in response to the assertion of a trigger signal (30) from a source such as a timer (63) or a central processing unit (61). As a result, data transfers can be more precisely related to a particular timing signal or set of timing signals.

Abstract: A timekeeping integrated circuit with devices partitioned into areas with different power supplies and level translators between the areas; the level translators use a memory cell for isolation and to shorten the signal active time for low power consumption. Also a one-wire communication port with low power input buffers may be used to detect very slowly varying voltages. The input buffers include staged decreasing resistors as a power dissipation limitation.

Abstract: A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO.sub.-- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO.sub.-- RIPPLE shows that any rippling has been completed and that access is safe. Thus, transfer will occur or not, but will never be cut short.

Abstract: An integrated circuit with power-up-warning circuitry wherein time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by current sourced to a reference voltage circuit, and this reference voltage is used as follows: An inverter receives the reference voltage as an input, and switches when the power supply becomes high enough that the reference voltage appears as a "low" level. When this inverter switches, current begins to be sourced to a timing capacitor. After the timing capacitor has charged up to a predetermined level, the current source to the reference-voltage node is turned off, and the power-up-warning signal (which has been driven high by output buffers) is turned off.