Abstract: A planar polarizer feed network comprising a six port branch coupler having two input ports and four output ports. The output ports are designed to have the same amplitude while their phases are sequentially offset by 90 degrees when fed from a first input port or by minus 90 degrees when fed from a second input port. In one embodiment, each output port is coupled to an aperture coupled antenna array comprising four slots and four patch antenna elements. In this arrangement, an RF signal may be coupled to each of the two input ports to couple properly phased signals to each of the antenna elements to simultaneously form both right-hand and left-hand circularly polarized signal emitted from the planar array of antenna elements.

Abstract: A planar polarizer feed network comprising a six port branch coupler having two input ports and four output ports. The output ports are designed to have the same amplitude while their phases are sequentially offset by 90 degrees when fed from a first input port or by minus 90 degrees when fed from a second input port. In one embodiment, each output port is coupled to an aperture coupled antenna array comprising four slots and four patch antenna elements. In this arrangement, an RF signal may be coupled to each of the two input ports to couple properly phased signals to each of the antenna elements to simultaneously form both right-hand and left-hand circularly polarized signal emitted from the planar array of antenna elements.

Abstract: A CMOS device is provided with a field shield region below one of the P and N channel MOS transistors, whereby the field shield region is formed to have the opposite conductivity of both the one MOS transistor it underlies, and of the substrate, thereby permitting the field shield region to be biased to a potential for turning off any anomalous back channel leakage current in the one MOS transistor, and also permitting the substrate to be biased to an opposite polarity for turning off such leakage current in the other MOS transistor.

Abstract: A memory cell has a first capacitance between a floating gate and a channel region and a second capacitance between a control gate and the floating gate. The second capacitance is less than said first capacitance, preferably much less, and there is self-alignment in two directions, resulting in a compact cell. The floating gate can have a textured surface facing the control gate. The control gate can also shift the cell operation from the enhancement mode into the depletion mode.

Abstract: A compact memory has a plurality of memory cells that are serially coupled. The plurality of cells are capacitively coupled to a substrate and directly coupled to switching circuits at both of its ends, which can disconnect the plurality of cells from a bit line at one end and a ground bus at the other end. An inhibit operation comprises precharging an array of pluralities of cells and the discharging of a selected plurality of cells. A WRITE operation comprises turning ON non-selected cells and then applying a programming voltage to a selected cell.

Abstract: A process is provided for forming a patterned layer of a polymeric material on a substrate for the lithographic processing thereof. A layer of polymeric material is formed on the substrate, embossed to form a pattern of peaks and valleys and dry etched to remove the residual polymeric material in the valleys, thereby exposing a portion of the substrate surface.

Abstract: A grid pattern for a solar cell of the type including a base layer of one conductivity type and an emitter layer of opposite conductivity type. The solar cell may have a square face and in this case the grid pattern is in the form of four symmetrical sub-patterns, each in a different quadrant of the square. Each such sub-pattern comprises a set of nested V shaped grid conductors, the apices of which lie on a common diagonal of the square and the ends of which connect to a common bus conductor at the peripheral edge of the square. Within each quadrant, the sub-pattern comprises a symmetrical pattern relative to a diagonal of the square. The pattern reduces the effect of line and sheet resistance and thereby permits more of the photon induced charge carriers to be collected and also permits a relatively large part of the cell face area to be available for the reception of photons.