Abstract: A power bus terminator circuit for use with personal computers and the like is designed to hold the circuit termination pins at a pre-established voltage while dissipating a relatively small amount of power (approximately 20 mW) during steady state operation. This is accomplished by connecting sets of first and second high impedance resistors together at a terminal, and in series between the bus terminator pins. Each of the terminals is connected through a relatively low value resistor to each one of the circuit termination pins, and through a capacitor, to one of the bus terminals to permit high-speed operation of the AC switching transitions of the circuits coupled to the termination pins. A relatively low amount of power (approximately another 30 mW or so) is consumed during the transitions of the signals appearing on the termination pins. The circuit results in a power dissipation reduction of between 90% to 75% over standard bus terminator circuits.