Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: The invention provides a method and an apparatus for enabling a user to determine whether a defective location in a memory device of an integrated circuit (IC) has been remapped to a location in a redundant memory portion of the memory device. Users are provided with the ability to observe the remapping, and preferably, to determine which locations in the memory device have been remapped. The memory device includes remapping observation logic that causes bits associated with remapping to be output from the memory device. Preferably, a computer receives the remapping bits and displays a description of any remapping on a display monitor. Therefore, not only is a user able to determine whether remapping has occurred, but also which locations in the memory device have been remapped.

Abstract: An apparatus for the on-chip testing of random access memory arrays. In representative embodiments, embedded circuitry provides the ability to test random access memory arrays on-chip without requiring substantial area on the chip. The circuits are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

Abstract: The invention provides a method and an apparatus for enabling a user to determine whether a defective location in a memory device of an integrated circuit (IC) has been remapped to a location in a redundant memory portion of the memory device. Users are provided with the ability to observe the remapping, and preferably, to determine which locations in the memory device have been remapped. The memory device includes remapping observation logic that causes bits associated with remapping to be output from the memory device. Preferably, a computer receives the remapping bits and displays a description of any remapping on a display monitor. Therefore, not only is a user able to determine whether remapping has occurred, but also which locations in the memory device have been remapped.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In repesentative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In repesentative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip testing random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to test random access memory arrays on-chip by means that do not required substantial area on the chip. The circuits disclosed are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

Abstract: A geometry accelerator for a computer graphics system performs transformations on vertex data representative of graphics primitives, decomposes quadrilaterals into triangles, and performs lighting, clipping and plane equation calculations for each primitive. The geometry accelerator incorporates a memory mapping technique that achieves high efficiency transfer of vertex information from the host computer to the geometry accelerator. A double buffered vertex RAM with granularity permits the quantity of data transferred to the geometry accelerator to be reduced. The transformation and decomposition engines of the geometry accelerator employ data management techniques in which calculations for shared vertices and shared edges of primitives are performed only once.

Abstract: A graphics processing circuit for use in a graphics accelerator that includes a clipping processor, with a vertex input data path operatively connected to a vertex data input of the clipping processor. A clipping preprocessor has a vertex data input operatively connected to the vertex input data path and a control output operatively connected to a control input of the clipping processor. The clipping preprocessor is constructed and arranged to perform an evaluation of a relationship between primitive vertex data from the vertex input data path and a clip region and to provide a signal on the control output based on this evaluation.

Abstract: A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit.