Abstract: A data storage device and method for improving the performance of data storage devices examines a command queue and performs data transfers to memory within the device before prior commands have completed. A process running in the idle loop of the controller in the storage device checks the queue for write requests and if a cache space within a dual-port cache to hold the transfer data is available, the data transfer portion of the transfer is completed, while the device is still waiting for completion of prior commands in the queue, and data transfers are completing from the cache to the physical media for the prior command.

Abstract: A method for prefetching data for a cache memory from a mass-storage device having a controller that executes a plurality of reordered commands. The method includes predetermining an extra time interval for each of the plurality of reordered commands. Next, prior to executing the next reordered command, data located subsequent to data requested from a committed command is prefetched utilizing the predetermined extra time interval of the next command. In a related embodiment, the method includes executing a command reordering algorithm during which the seek and latency time periods of each of the plurality of reordered commands is computed.

Abstract: In a method of and a system for managing reselection of an initiator by a target on a SCSI bus, the target attempts to secure control of the bus for a first reselection cycle to reselect the initiator. If the target fails to secure control of the bus for the first reselection cycle and the target is selected by the initiator for a selection cycle, the target processes the selection cycle. However, concurrently with processing the selection cycle, substantially immediately after the bus becomes free, and before the target completes processing the selection cycle, the target attempts to secure control of the bus for a second reselection cycle to reselect the initiator.

Abstract: A method and apparatus are provided for implementing automatic cache variable update. A cache variable update hardware maintains a plurality of variables indicative of a data segment in the cache. The plurality of variables include a segment state variable, a segment starting address variable, a segment length variable and a segment offset variable. The cache variable update hardware monitors the cache to identify a selection of a segment for a data transfer to and from the cache and to identify data transfers. The plurality of variables are initialized responsive to an identified cache search. The segment length variable is incremented responsive to a data block written to the cache. The segment state variable is modified responsive to a data transfer complete.