Patents by Inventor Louise DE CONTI

Louise DE CONTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916061
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 27, 2024
    Assignee: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Patent number: 11581303
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Patent number: 11387354
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Louise De Conti
  • Patent number: 11296072
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 5, 2022
    Assignee: STMicroelectronics SA
    Inventors: Thomas Bedecarrats, Louise De Conti, Philippe Galy
  • Publication number: 20200357902
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • Publication number: 20200357788
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise DE CONTI, Philippe GALY
  • Publication number: 20200013901
    Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Publication number: 20200006320
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Louise DE CONTI, Philippe GALY
  • Publication number: 20190181131
    Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI