Patents by Inventor Louise Margaret Jameson

Louise Margaret Jameson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system
    Patent number: 7979822
    Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: July 12, 2011
    Assignee: ARM Limited
    Inventors: Andrew Mark Nightingale, Louise Margaret Jameson
  • Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system
    Publication number: 20080313587
    Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 18, 2008
    Applicant: ARM LIMITED
    Inventors: Andrew Mark Nightingale, Louise Margaret Jameson