Abstract: A method for measuring the forward power output of an amplifier with improved accuracy with a mismatched load based on probing the amplitude of the AC voltage and current in the final amplifier stage. Amplitudes are combined resulting in a composite reading that is affected less by load mismatch. Variations include measuring signal amplitude at two points 90 degrees apart in the transmission medium and measuring the power supply voltage and current of a saturated amplifier.

Abstract: A method for measuring the forward power output of an amplifier with improved accuracy with a mismatched load based on probing the amplitude of the AC voltage and current in the final amplifier stage. Amplitudes are combined resulting in a composite reading that is affected less by load mismatch. Variations include measuring signal amplitude at two points 90 degrees apart in the transmission medium and measuring the power supply voltage and current of a saturated amplifier.

Abstract: A power amplifier circuit includes an adjustable gain power amplifier for amplifying an RF input signal. An isolated node in the adjustable gain power amplifier is isolated from the output load by a gain stage of the adjustable gain power amplifier. The power level of a signal at the isolated node corresponds to the power level of a signal at the output load. A detector is either capacitively coupled to the isolated node or connected by a direct current (DC) connection. The detector detects the power level of the signal at the isolated node. The detector generates a power level indicator that is sent to a gain control circuit. The gain control circuit adjusts the gain of the adjustable gain power amplifier to maintain a constant drive level at the isolated node.

Abstract: A power splitter receives power and has a first and second power output. The first power output is connected first power limiting section. A first matching circuit connects between an output of the first power limiting section and a first phase shifter. A second phase shifter connects between the second power output and a second power limiting section. An output of the second limiting section connects to a second matching circuit. A power combiner receives the output of the first phase shifter and the second matching circuit output. The power from the power combiner is delivered to the load.

Abstract: A method for measuring the forward power output of an amplifier with improved accuracy with a mismatched load based on probing the amplitude of the AC voltage and current in the final amplifier stage. Amplitudes are combined resulting in a composite reading that is affected less by load mismatch. Variations include measuring signal amplitude at two points 90 degrees apart in the transmission medium and measuring the power supply voltage and current of a saturated amplifier.

Abstract: A sampling apparatus for use in high data rate jitter measurement systems based on offset sampling uses a trigger circuit, along with a time-based variable delay, to align a sampling strobe to drive two samplers. An input data signal is split and fed via separate signal paths into the two samplers. One of the samplers is delayed in sampling the input signal or the input is delayed to one of the samplers, such that the two samples of the input signal are offset in time. The jitter present in the SUT can be calculated using the two samples. In addition, when using two strobe circuits, the jitter inherently present in the strobe circuits can be compensated for by offset sampling a reference clock with each main strobe to determine the phase and cycle number of the reference clock at each strobe time.

Abstract: Error-related information acquired using a bit error ratio detector (BERT) is extrapolated on the basis of prior testing, in which measurements “superior” to those acquired by the BERT are used to provide an initial extrapolation calibration. For example, measures of data dependent jitter acquired by a digital communications analyzer (DCA) may be used to offset the less accurate jitter-related measures by the BERT. As a consequence, the benefits of a DCA and a BERT are combined, while using only the BERT.

Abstract: Repetitive sampling of a data signal is performed. A clock reference is generated. The clock reference has a known period relationship with the data signal. The clock reference and the data signal are simultaneously sampled. The sampled information from the clock reference is used to determine in what phase of the clock reference sampled values of the data signal occur.

Abstract: A sampling apparatus for use in high data rate jitter measurement systems based on offset sampling is disclosed. A trigger circuit is used, along with a time-based variable delay, to align a sampling strobe to drive two samplers. An input data signal is split and fed via separate signal paths into the two samplers. One of the samplers is delayed in sampling the input signal or the input is delayed to one of the samplers, such that the two samples of the input signal are offset in time. The jitter present in the SUT can be calculated using the two samples. In addition, when using two strobe circuits, the jitter inherently present in the strobe circuits can be compensated for by offset sampling a reference clock with each main strobe to determine the phase and cycle number of the reference clock at each strobe time.

Abstract: Repetitive sampling of a data signal is performed. A clock reference is generated. The clock reference has a known period relationship with the data signal. The clock reference and the data signal are simultaneously sampled. The sampled information from the clock reference is used to determine in what phase of the clock reference sampled values of the data signal occur.