Abstract: An efficient and automated algorithm for placing power gating switches within a voltage island of an integrated circuit, which ensures compliance with defined electrical specifications. A power gating switch is placed in every legal location on the integrated circuit and the minimum number of power gating switches is calculated based on current requirements of the voltage island. Each power gating switch is modeled as an ideal resistor whose value is obtained from the slope of the I-V curve of the switch when operating in the linear region. The power distribution networks of the integrated circuit and the voltage island are extracted and modeled as a resistive network. Circuit macros placed within the voltage island are modeled as current sources. The extracted linear network is then simulated using a DC stimulus to obtain expected voltage drops across the voltage island as well as the currents in all branches of the voltage island power grid and through each power gating switch.

Abstract: An efficient and automated algorithm for placing power gating switches within a voltage island of an integrated circuit, which ensures compliance with defined electrical specifications. A power gating switch is placed in every legal location on the integrated circuit and the minimum number of power gating switches is calculated based on current requirements of the voltage island. Each power gating switch is modeled as an ideal resistor whose value is obtained from the slope of the I-V curve of the switch when operating in the linear region. The power distribution networks of the integrated circuit and the voltage island are extracted and modeled as a resistive network. Circuit macros placed within the voltage island are modeled as current sources. The extracted linear network is then simulated using a DC stimulus to obtain expected voltage drops across the voltage island as well as the currents in all branches of the voltage island power grid and through each power gating switch.

Abstract: A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.

Abstract: A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.