Abstract: The present invention relates to a light-emitting diode (LED) structure, comprising a flexible substrate and one or a plurality of chip-scale package (CSP) LED chips. The flexible substrate includes a metal layer as the core, and the metal layer is coated with a ceramic insulating layer. The flexible substrate is provided with a plurality of electrodes. The CSP LED chips are provided on the flexible substrate, with the electrical connection units of each CSP LED chip electrically connected to the corresponding electrodes on the flexible substrate respectively.

Abstract: A radio frequency identification tag includes a housing shaped as a stripe defining a longitudinal side and an inlay disposed within the housing. The inlay includes a carrier board supporting a packaged chip and a wiring antenna in connection with the packaged chip. The wiring antenna is formed with an electrical joint directly and electrically connecting the packaged chip and an extension portion directly extending out of the electrical joint. The extension direction of the extension portion is substantially perpendicular to the longitudinal side.

Abstract: A light emitting diode and a method of the same are provided. The light emitting diode includes a substrate with a first region and a second region, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The light emitting diode further includes a plurality of vias, a first metal layer, a second metal layer, and a patterned passivation layer interposed between the second semiconductor layer and the first metal layer. The plurality of vias are located in the first region and penetrate through the second semiconductor layer and the light-emitting layer to expose part of the first semiconductor layer. The first metal layer is located in the first region, and electrically contacted with the first semiconductor layer through the plurality of vias. The second metal layer is located in the second region, and electrically contacted with the second semiconductor layer and electrically insulated from the first metal layer.

Abstract: A chip package of the present invention including a substrate, a chip, at least one electrical connecting element and a solder layer is provided. The substrate has at least one contact. The chip is disposed on the substrate and has at least one pad. The electrical connecting element includes a copper bump and an anti-oxidation layer. The copper bump is disposed on the pad. The anti-oxidation layer is disposed on at least part of an outside surface of the copper bump and the outside surface of the copper bump is not connected to the pad. The solder layer is disposed between the copper bump and the contact. The pad is electrically connected to the contact through the electrical connecting element and solder layer. In addition, a chip element of the present invention is also provided.

Abstract: A radio frequency identification tag includes a housing shaped as a stripe defining a longitudinal side and an inlay disposed within the housing. The inlay includes a carrier board supporting a packaged chip and a wiring antenna in connection with the packaged chip. The wiring antenna is formed with an electrical joint directly and electrically connecting the packaged chip and an extension portion directly extending out of the electrical joint. The extension direction of the extension portion is substantially perpendicular to the longitudinal side.

Abstract: A test module and method for radio frequency identification (RFID) chips are provided. The test module includes a test head having a chip carrier for carrying a RFID chip to be tested, the chip carrier having a first antenna electronically connecting the RFID chip. The module further includes a second antenna for communicating with the first antenna; and a base supporting the chip carrier and the second antenna. The test module further includes a test computer electronically connecting the second antenna, wherein the test computer evaluates functions of the RFID chip by way of the communications between the first antenna and the second antenna.

Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.

Abstract: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When connecting the cable to a task object such as an LCD glass substrate or PCB, only a usual non-conductive paste is applied to join the cable and the task object, without use of expensive anisotropic-conductive paste or film.

Abstract: The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the extendable substrate, the second surface being opposite to the first surface; forming multiple recesses in the wafer for separating the integrated circuit devices from each other; elongating the extendable substrate to enlarge the multiple recesses; and forming an insulating layer to fill the recesses and cover multiple integrated circuit devices.

Abstract: A method for manufacturing an integrated circuit device having antenna conductors is provided. The method includes the steps of providing a wafer with a plurality of integrated circuit components; forming a first antenna conductor on the surface of each integrated circuit component; forming a plurality of metal bumps above the first antenna conductor; coating an insulating layer to encapsulate the plurality of integrated circuit components and to cover the plurality of metal bumps; removing a portion of the insulating layer to expose a top portion of each metal bump; and forming a second antenna conductor on the insulating layer by screen printing.

Abstract: A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it.

Abstract: A method for manufacturing an integrated circuit device having antenna conductors is provided. The method includes the steps of providing a wafer with a plurality of integrated circuit components; forming a first antenna conductor on the surface of each integrated circuit component; forming a plurality of metal bumps above the first antenna conductor; coating an insulating layer to encapsulate the plurality of integrated circuit components and to cover the plurality of metal bumps; removing a portion of the insulating layer to expose a top portion of each metal bump; and forming a second antenna conductor on the insulating layer by screen printing.

Abstract: A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of integrated circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of integrated circuit devices and on a sidewall of it.

Abstract: A method for manufacturing an integrated circuit device having antenna conductors is provided. The method includes the steps of providing a wafer with a plurality of integrated circuit components; forming a first antenna conductor on the surface of each integrated circuit component; forming a plurality of metal bumps above the first antenna conductor; coating an insulating layer to encapsulate the plurality of integrated circuit components and to cover the plurality of metal bumps; removing a portion of the insulating layer to expose a top portion of each metal bump; and forming a second antenna conductor on the insulating layer by screen printing.

Abstract: A test module and method for radio frequency identification (RFID) chips are provided. The test module includes a test head having a chip carrier for carrying a RFID chip to be tested, the chip carrier having a first antenna electronically connecting the RFID chip. The module further includes a second antenna for communicating with the first antenna; and a base supporting the chip carrier and the second antenna. The test module further includes a test computer electronically connecting the second antenna, wherein the test computer evaluates functions of the RFID chip by way of the communications between the first antenna and the second antenna.

Abstract: A light emitting diode and a method of the same are provided. The light emitting diode includes a substrate with a first region and a second region, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The light emitting diode further includes a plurality of vias, a first metal layer, a second metal layer, and a patterned passivation layer interposed between the second semiconductor layer and the first metal layer. The plurality of vias are located in the first region and penetrate through the second semiconductor layer and the light-emitting layer to expose part of the first semiconductor layer. The first metal layer is located in the first region, and electrically contacted with the first semiconductor layer through the plurality of vias. The second metal layer is located in the second region, and electrically contacted with the second semiconductor layer and electrically insulated from the first metal layer.

Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.

Abstract: The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the extendable substrate, the second surface being opposite to the first surface; forming multiple recesses in the wafer for separating the integrated circuit devices from each other; elongating the extendable substrate to enlarge the multiple recesses; and forming an insulating layer to fill the recesses and cover multiple integrated circuit devices.

Abstract: A packaging method for an electronic element has: etching portions of a top surface of a metal board to form recesses between raised unetched segments and filling the recesses with a dielectric material of high density polymer; forming multiple solder balls respectively on the raised unetched segments; coating the solder balls with a thin flux layer; bonding contacts on a die respectively to the solder balls with the thin flux layer; injecting an encapsulant between the die and the metal board; sealing the die with an outer encapsulant; etching a bottom surface of the metal board to form multiple metal leads; coating the bottom surface of the metal board other than the metal leads with a solder resist; and conducting a continuity test. The solder balls are not formed directly on the fragile die so the packaging method can be used with any types of dies and has a good applicability.

Abstract: A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of integrated circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of integrated circuit devices and on a sidewall of it.