Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including memory pages, a memory controller coupled to the memory device. The memory controller is configured to send, to the memory device, a first command indicating to identify dummy data, and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.

Abstract: A memory device includes: a memory cell array comprising memory cells, wherein a preset number of the memory cells form a codeword; and a peripheral circuit coupled to the memory cell array and configured to: receive a read retry command for instructing to obtain target data stored in a target codeword; obtain a valley bottom voltage in response to the read retry command, wherein the valley bottom voltage is used as a read voltage when performing a read operation on the target codeword; and perform the read operation on the target codeword based on the valley bottom voltage to obtain the target data.

Abstract: Examples of the disclosure provide a memory system, including: at least one memory device and a controller coupled to and configured to control the memory device, the memory device includes a memory cell array and a peripheral circuit coupled thereto, the memory cell array includes a plurality of memory cells, in which a preset number of memory cells form a codeword; the peripheral circuit is configured to: perform a read operation on a reference codeword to obtain a first result, which is used as a VT indicator; and the controller is configured to: obtain at least one offset prediction according to the VT indicator in combination with a mapping table, the mapping table includes a mapping relationship between the VT indicator and the offset prediction; and determine, according to the offset prediction, a valley voltage being used as a read voltage for performing the read operation on a target codeword.

Abstract: A memory device, a memory system and a control method thereof to identify a programming state of memory cells includes an example memory device with a memory block including a plurality of memory cells; a plurality of word lines coupled to the memory block; and a peripheral circuit coupled to the plurality of word lines and configured to: perform a first programming operation in response to a first operation command to program first memory cells; perform a first verification operation to obtain the first number of second memory cells that are coupled to the first word line, have an erased state as the target state and have a threshold voltage larger than a first verification voltage, which is a verification voltage of the first programmed state; and generate a first state identifier indicating a programming failure in response to the first number being larger than a first threshold.

Abstract: Examples of the present application disclose a memory device. The memory device includes: a memory cell array comprising memory cells that store a plurality of memory bits, the plurality of memory bits corresponding to a plurality of orders of read voltages, and a preset number of the memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: acquire a first result of at least one code word corresponding to a target read voltage of a target order; acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located; and determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order.

Abstract: Examples of the present disclosure disclose a memory device, a memory system, a memory controller and an operating method, the memory device includes: a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage corresponding to the second stage is less than the read voltage in the first stage; peripheral circuit coupled to the array of memory cells and configured to: obtain the target valley voltage in the first target stage; take the target valley voltage as a read voltage at which a read operation is performed on the at least one code word; and obtain the predicted valley voltage in the second target stage in accordance with the target valley voltage in the first target stage.

Abstract: According to one aspect of the present disclosure, a memory system is provided. The memory system may include at least one memory. The at least one memory may include a memory array coupled to n wordlines. The n wordlines may be sequentially arranged by physical wordline identifiers, where n?2. The memory system may include a memory controller coupled to the at least one memory. The memory controller may obtain multiple pieces of data to be written into the memory array. The memory controller may map n physical wordline identifiers to n virtual wordline identifiers. The physical wordline identifiers may respectively correspond to m adjacent virtual wordline identifiers spaced apart from each other, where 2?m ?n. The memory controller may generate check data based on data corresponding to the m adjacent virtual wordline identifiers. The check data may check and recover the data corresponding to the m adjacent virtual wordline identifiers.

Abstract: Examples of the present disclosure provide memory systems and methods of operating thereof, computer-readable storage mediums and electronic apparatuses. An example memory system includes: a memory including a plurality of blocks, wherein the block includes a plurality of physical pages; and a memory controller coupled with the memory and configured to: determine a sum of the numbers of read times of physical pages adjacent to a first target physical page in a first block among the plurality of blocks; and in response to the sum of the numbers of read times being greater than or equal to a first threshold, move data stored in the first target physical page to a second block among the plurality of blocks, wherein the second block is different from the first block.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including memory pages, a memory controller coupled to the memory device. The memory controller is configured to send, to the memory device, a first command indicating to identify dummy data, and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.

Abstract: This disclosure provides memory, storage system, and operating method for memory. In an implementation, a method comprising: receiving an operation instruction from the controller; mapping a plurality of initial word line identifiers in the operation instruction to a plurality of physical word line identifiers; performing the operation corresponding to the operation instruction on the plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers; wherein, at least one of third-type memory cell rows is distributed between the first memory cell rows and the second memory cell rows in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to the same parity data.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including one or more memory pages, and a memory controller coupled to the memory device. The memory controller is configured to perform operations including obtaining a read window corresponding to the one or more memory pages, and determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages.

Abstract: Examples of the present disclosure provide a memory system and operating method thereof, storage medium. Wherein the memory system includes: a memory device including multiple memory cells, a preset number of the memory cells forming a codeword; a memory controller coupled to the memory device and configured to: obtain a first read result of the codeword at a first read level; according to the decoding failure of the first read result, obtain a second read result of the codeword at a second read level, wherein the first read level is different from the second read level; and perform decoding processing on the second read result based on the flipping result, wherein the flipping result includes information of the bits of the codeword flipped in the first read result and the second read result.

Abstract: According to one aspect of the present disclosure, a memory system is provided. the memory system may include at least one memory. The at least one memory may include a memory array coupled to n wordlines. The n wordlines may be sequentially arranged by physical wordline identifiers, where n?2. The memory system may include a memory controller coupled to the at least one memory. The memory controller may obtain multiple pieces of data to be written into the memory array. The memory controller may map n physical wordline identifiers to n virtual wordline identifiers. The physical wordline identifiers may respectively correspond to m adjacent virtual wordline identifiers spaced apart from each other, where 2?m?n. The memory controller may generate check data based on data corresponding to the m adjacent virtual wordline identifiers. The check data may check and recover the data corresponding to the m adjacent virtual wordline identifiers.

Abstract: An example of the present disclosure provides a memory device including: a memory array and a peripheral circuit coupled with the memory array. The memory array includes memory blocks each including pages each including memory cells. The peripheral circuit includes a control logic configured to: receive the first information indicating to search the boundary page of the selected memory block in the memory blocks; the boundary page being related to the page requiring information recovery in the selected memory block; receive the address of the selected memory block; obtain the address of the boundary page in connection with the page erasing check function using the address of the selected memory block, the page erasing check function being configured to feed back whether memory cells in the page to be checked are all in the erased state.

Abstract: Example memory devices, memory systems, and methods for identifying zero pages in a memory device are disclosed. In one example, a method of operating a memory device includes performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, the failed memory cells being memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including memory pages, a memory controller coupled to the memory device. The memory controller is configured to send, to the memory device, a first command indicating to identify dummy data, and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.

Abstract: Methods, computer programs, and systems are disclosed, with one method including characterizing a depth variation of a predicted result within a feature of a pattern from a lithography simulation. The method evaluates the depth variation characterization and selects patterns or gauges based on the depth variation evaluation. In some embodiments, the evaluating can be based on an aerial image (AI) depth sensitivity having the depth variation.

Abstract: A sound signal processing method and a headset device. A target filter and a first audio processing unit are added. The target filter processes an external sound signal collected by an external microphone, to obtain an environmental sound attenuation signal and a voice attenuation signal. The first audio processing unit removes, based on the environmental sound attenuation signal and the voice attenuation signal, a second external environmental sound signal and a second voice signal from an in-ear sound signal collected by an error microphone, to obtain a blocking signal, and transmits the blocking signal to a feedback filter. The feedback filter may generate an inverted noise signal corresponding to the blocking signal and play the inverted noise signal through a speaker.

Abstract: This disclosure provides memory, storage system, and operating method for memory. In an implementation, a method comprising: receiving an operation instruction from the controller; mapping a plurality of initial word line identifiers in the operation instruction to a plurality of physical word line identifiers; performing the operation corresponding to the operation instruction on the plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers; wherein, at least one of third-type memory cell rows is distributed between the first memory cell rows and the second memory cell rows in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to the same parity data.

Abstract: An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.