Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including one or more memory pages, and a memory controller coupled to the memory device. The memory controller is configured to perform operations including obtaining a read window corresponding to the one or more memory pages, and determining, based on the read window, an erase/program (E/P) cycle status of the one or more memory pages.

Abstract: Examples of the present disclosure provide a memory system and operating method thereof, storage medium. Wherein the memory system includes: a memory device including multiple memory cells, a preset number of the memory cells forming a codeword; a memory controller coupled to the memory device and configured to: obtain a first read result of the codeword at a first read level; according to the decoding failure of the first read result, obtain a second read result of the codeword at a second read level, wherein the first read level is different from the second read level; and perform decoding processing on the second read result based on the flipping result, wherein the flipping result includes information of the bits of the codeword flipped in the first read result and the second read result.

Abstract: According to one aspect of the present disclosure, a memory system is provided. the memory system may include at least one memory. The at least one memory may include a memory array coupled to n wordlines. The n wordlines may be sequentially arranged by physical wordline identifiers, where n?2. The memory system may include a memory controller coupled to the at least one memory. The memory controller may obtain multiple pieces of data to be written into the memory array. The memory controller may map n physical wordline identifiers to n virtual wordline identifiers. The physical wordline identifiers may respectively correspond to m adjacent virtual wordline identifiers spaced apart from each other, where 2?m?n. The memory controller may generate check data based on data corresponding to the m adjacent virtual wordline identifiers. The check data may check and recover the data corresponding to the m adjacent virtual wordline identifiers.

Abstract: An example of the present disclosure provides a memory device including: a memory array and a peripheral circuit coupled with the memory array. The memory array includes memory blocks each including pages each including memory cells. The peripheral circuit includes a control logic configured to: receive the first information indicating to search the boundary page of the selected memory block in the memory blocks; the boundary page being related to the page requiring information recovery in the selected memory block; receive the address of the selected memory block; obtain the address of the boundary page in connection with the page erasing check function using the address of the selected memory block, the page erasing check function being configured to feed back whether memory cells in the page to be checked are all in the erased state.

Abstract: Example memory devices, memory systems, and methods for identifying zero pages in a memory device are disclosed. In one example, a method of operating a memory device includes performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, the failed memory cells being memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including memory pages, a memory controller coupled to the memory device. The memory controller is configured to send, to the memory device, a first command indicating to identify dummy data, and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.

Abstract: Methods, computer programs, and systems are disclosed, with one method including characterizing a depth variation of a predicted result within a feature of a pattern from a lithography simulation. The method evaluates the depth variation characterization and selects patterns or gauges based on the depth variation evaluation. In some embodiments, the evaluating can be based on an aerial image (AI) depth sensitivity having the depth variation.

Abstract: A sound signal processing method and a headset device. A target filter and a first audio processing unit are added. The target filter processes an external sound signal collected by an external microphone, to obtain an environmental sound attenuation signal and a voice attenuation signal. The first audio processing unit removes, based on the environmental sound attenuation signal and the voice attenuation signal, a second external environmental sound signal and a second voice signal from an in-ear sound signal collected by an error microphone, to obtain a blocking signal, and transmits the blocking signal to a feedback filter. The feedback filter may generate an inverted noise signal corresponding to the blocking signal and play the inverted noise signal through a speaker.

Abstract: This disclosure provides memory, storage system, and operating method for memory. In an implementation, a method comprising: receiving an operation instruction from the controller; mapping a plurality of initial word line identifiers in the operation instruction to a plurality of physical word line identifiers; performing the operation corresponding to the operation instruction on the plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers; wherein, at least one of third-type memory cell rows is distributed between the first memory cell rows and the second memory cell rows in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to the same parity data.

Abstract: An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.

Abstract: Examples of the present disclosure include a memory device including: a memory cell array including a plurality of blocks. The blocks include a plurality of word lines, and a plurality of memory cells coupled to the plurality of word lines. The plurality of memory cells coupled to a same word line form a physical page. A physical page includes one or more code words; and a peripheral circuit coupled to the memory cell array and configured to: acquire a predicted initial read voltage of the one or more code words according to a position of the word line coupled to the one or more code words in an open block and a position of a first blank physical page in the open block; and obtain a target valley voltage of the code words according to a first result corresponding to the code words at the predicted initial read voltage.

Abstract: According to one aspect, a memory system is provided. The memory system may include a memory device and a memory controller coupled to the memory device. The memory controller may be configured to in response to a power-down during a first programming operation, encode to-be-written data corresponding to the first programming operation to obtain encoded data, and write the encoded data into the memory device. Wherein the to-be-written data is data to be written into the memory device through the first programming operation. An amount of the encoded data is less than an amount of the to-be-written data. In response to a power-on after the power-down, decode the obtained encoded data and the written data corresponding to the first programming operation to obtain at least a portion of error recovery data corresponding to the written data.

Abstract: An example of the present disclosure provides a memory device including: a memory array and a peripheral circuit coupled with the memory array. The memory array includes memory blocks each including pages each including memory cells. The peripheral circuit includes a control logic configured to: receive the first information indicating to search the boundary page of the selected memory block in the memory blocks; the boundary page being related to the page requiring information recovery in the selected memory block; receive the address of the selected memory block; obtain the address of the boundary page in connection with the page erasing check function using the address of the selected memory block, the page erasing check function being configured to feed back whether memory cells in the page to be checked are all in the erased state.

Abstract: Examples of the present disclosure provide a memory system and operating method thereof, and storage medium; wherein the memory system includes: a memory controller configured to send a first command, the first command including first data; and a memory device including a latch; the memory device coupled to the memory controller and configured to: receive the first command; in response to the first command, perform a logical operation on the first data with the latch to obtain parity data.

Abstract: The present disclosure provides a memory device and an operation method thereof, a memory system and an operation method thereof, and an electronic apparatus. The memory device includes a memory array and a peripheral circuit coupled with the memory array; the peripheral circuit is configured to: in response to a characteristic parameter setting command, receive a characteristic parameter of an erased page checking operation, wherein the characteristic parameter of the erased page checking operation includes at least a read voltage compensation parameter of the erased page checking operation; and in response to an erased page checking command, perform the erased page checking operation on the memory array based on the characteristic parameter of the erased page checking operation.

Abstract: An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.

Abstract: The present application provides a memory system, an operation method of a memory system, and a memory controller, and relates to the technical field of storage. In the solution provided by the present application, a memory comprises a plurality of blocks and at least one reserved block. Upon detecting a fail page among pages included in the plurality of blocks, a memory controller can acquire data in the fail page, and back up the data in the fail page to one backup page in the at least one reserved block.

Abstract: The present disclosure relates to codon-optimized sequences coding for hGCDH polypeptide and recombinant adeno-associated virus (rAAV) vectors comprising one of said sequences under the control of a promoter component. Also provided herein are viral particles comprising the rAAV vector, a pharmaceutical composition comprising the rAAV vector or the viral particles, and uses thereof in treating Glutaric aciduria type I (GA-I).

Abstract: According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

Abstract: Examples of the present disclosure provide a memory system and operating method thereof, storage medium. Wherein the memory system includes: a memory device including multiple memory cells, a preset number of the memory cells forming a codeword; a memory controller coupled to the memory device and configured to: obtain a first read result of the codeword at a first read level; according to the decoding failure of the first read result, obtain a second read result of the codeword at a second read level, wherein the first read level is different from the second read level; and perform decoding processing on the second read result based on the flipping result, wherein the flipping result includes information of the bits of the codeword flipped in the first read result and the second read result.