Abstract: A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

Abstract: An analog-to-digital conversion circuit, an electronic apparatus, and an operation method are provided. The analog-to-digital conversion circuit includes: An analog-to-digital conversion circuit, including: a clamping module, coupled to a load circuit through a clamping point, where the load circuit provides a load current during working; a bias current generation module, coupled to the clamping module through the clamping point and configured to provide a bias current to the clamping point; and a quantization module, coupled to the clamping module through the clamping point and a first node, configured to provide a bias voltage to the clamping module through the first node to obtain a clamping branch current that is input into the clamping point, and further configured to provide a first current to the clamping point and regulate the first current based on a comparison result of the bias current and the clamping branch current to quantize the load current.

Abstract: The present disclosure relates to the field of analog to digital conversion, and provides an analog to digital conversion circuit, a chip and electronic apparatus. The circuit comprises a clock signal generator, a converter, and a feedback circuit, wherein a power supply voltage of the clock signal generator, the converter, and the feedback circuit is less than or equal to a first threshold, the clock signal generator configured to generate at least one pair of clock signals with a swing greater than the first threshold, and output the clock signals to the converter to drive at least a part of the converter, the converter configured to obtain a digital output signal based on an analog input signal and a feedback signal, and the feedback circuit configured to generate the feedback signal based on a latest digital output signal and output the feedback signal to the converter.

Abstract: A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

Abstract: A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

Abstract: In one example, an apparatus comprises: a photodiode configured to generate a charge in response to light within an exposure period, a charge sensing unit configured to accumulate at least a part of the charge as an overflow charge, a quantizer, and a controller configured to: within a first time within the exposure period, control the quantizer to perform a first quantization operation to quantize the overflow charge accumulated at the charge sensing unit to generate a first measurement output; within a second time after the first time, and within the exposure period, control the quantizer to perform a second quantization operation to quantize the overflow charge accumulated at the charge sensing unit to generate a second measurement output; and generate a digital output to represent an intensity of the light based on at least one of the first measurement output or the second measurement output.

Abstract: A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency.