Abstract: An electrical connector includes an insulative housing and a number of terminals retained in the insulative housing. The insulative housing has a mating surface, a mounting surface, and a slot going through the mounting surface. The terminal received in the slot includes an interference portion retained in the slot, a contacting portion disposed around the mating surface, and a soldering leg extending downwardly beyond the mounting surface. The interference portion has two barbs disposed at two opposite sides thereof, respectively. The terminal includes a blocking portion connecting between the interference portion and the soldering leg. The width of the blocking portion is greater than the width of the interference portion.

Abstract: An electrical connector includes an insulative housing and a number of terminals retained in the insulative housing. The insulative housing has a mating surface, a mounting surface, and a slot going through the mounting surface. The terminal received in the slot includes an interference portion retained in the slot, a contacting portion disposed around the mating surface, and a soldering leg extending downwardly beyond the mounting surface. The interference portion has two barbs disposed at two opposite sides thereof, respectively. The terminal includes a blocking portion connecting between the interference portion and the soldering leg. The width of the blocking portion is greater than the width of the interference portion.

Abstract: A card connector assembly includes a card connector and a pick-up cap attached to the card connector. The card connector includes an insulating housing and a plurality of conductive terminals The insulating housing has a base portion, a mating frame and a mating cavity formed in the mating frame. The conductive terminals have contacting sections and soldering sections. The pick-up cap has an adsorption portion and a retaining plate extending downwardly from a middle area of the adsorption portion and inserted into the mating cavity. The retaining plate has an interference portion protruding out of the retaining portion to abut against an inner surface of the mating frame.

Abstract: A card connector includes an insulating housing, a plurality of conductive terminals and a retaining plate. The insulating housing has a base portion, an upper face, a lower face, a mating frame with a mating cavity which has a mating face parallel to the lower face. The conductive terminals have contacting portions extending into the mating cavity. The base portion has a retaining space recessed upwardly from the lower face and a platform located at the upper face of the base portion, and the retaining space upwardly runs through the platform. A stopping portion is formed between the retaining space and the mating frame. The retaining plate is retained in the retaining space and has a plurality of soldering legs extending downwardly out of the lower face and a latch portion extending upwardly and latching with the stopping portion.

Abstract: A system and method that facilitates urban traffic state detection based on support vector machine (SVM) and multilayer perceptron (MLP) classifiers is provided. Moreover, the SVM and MLP classifiers are fused into a cascaded two-tier classifier that improves the accuracy of the traffic state classification. To further improve the accuracy, the cascaded two-tier classifier (e.g., MLP-SVM), a single SVM classifier and a single MLP classifier are fused to determine a final decision for a traffic state. In addition, fusion strategies are employed during training and implementation phases to compensate for data acquisition and classification errors caused by noise and/or outliers.

Abstract: A system and method that facilitates urban traffic state detection based on support vector machine (SVM) and multilayer perceptron (MLP) classifiers is provided. Moreover, the SVM and MLP classifiers are fused into a cascaded two-tier classifier that improves the accuracy of the traffic state classification. To further improve the accuracy, the cascaded two-tier classifier (e.g., MLP-SVM), a single SVM classifier and a single MLP classifier are fused to determine a final decision for a traffic state. In addition, fusion strategies are employed during training and implementation phases to compensate for data acquisition and classification errors caused by noise and/or outliers.

Abstract: Disclosed are methods and systems for formulating a wirelength estimate that takes into account whether any of the routing directions are unavailable. Under certain circumstances, one or more of the routing layers may not be available for routing a wire. If this occurs, then the bounding box that is determined for performing the wirelength estimate would take into account the unavailability of the layer.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well, spread out the cells are in the placement.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.