Patents by Inventor Lu Sha

Lu Sha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7107556
    Abstract: Disclosed are methods and systems for formulating a wirelength estimate that takes into account whether any of the routing directions are unavailable. Under certain circumstances, one or more of the routing layers may not be available for routing a wire. If this occurs, then the bounding box that is determined for performing the wirelength estimate would take into account the unavailability of the layer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 12, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hussein Etawil, Krishna Belkhale, Lu Sha, Jonathan Frankle
  • Patent number: 6671859
    Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: December 30, 2003
    Assignee: Synopsys, Inc.
    Inventors: William C. Naylor, Ross Donelly, Lu Sha
  • Patent number: 6662348
    Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well, spread out the cells are in the placement.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: December 9, 2003
    Assignee: Synopsys, Inc.
    Inventors: William C. Naylor, Ross Donelly, Lu Sha
  • Patent number: 6301693
    Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: October 9, 2001
    Assignee: Synopsys, Inc.
    Inventors: William C. Naylor, Ross Donelly, Lu Sha
  • Patent number: 6282693
    Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: August 28, 2001
    Assignee: Synopsys, Inc.
    Inventors: William C. Naylor, Ross Donelly, Lu Sha