Patents by Inventor Lu-Sheng Chou
Lu-Sheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984353Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.Type: GrantFiled: June 21, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
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Publication number: 20240153987Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Patent number: 11916100Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: GrantFiled: March 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Publication number: 20230377957Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
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Publication number: 20230307492Abstract: In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Lu-Sheng Chou, Hsuan-Han Tseng, Chun-Yuan Chen, Hsiao-Hui Tseng, Ching-Chun Wang
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Publication number: 20230032620Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: ApplicationFiled: March 21, 2022Publication date: February 2, 2023Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Publication number: 20220246469Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.Type: ApplicationFiled: June 21, 2021Publication date: August 4, 2022Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
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Patent number: 10290723Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.Type: GrantFiled: May 17, 2018Date of Patent: May 14, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
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Publication number: 20180269308Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.Type: ApplicationFiled: May 17, 2018Publication date: September 20, 2018Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
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Patent number: 10008581Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.Type: GrantFiled: August 30, 2015Date of Patent: June 26, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
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Publication number: 20170040435Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.Type: ApplicationFiled: August 30, 2015Publication date: February 9, 2017Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
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Patent number: 9343026Abstract: Provided is the pixel circuit for active matrix display apparatus and the driving method thereof, which is controlled by digital signal. The pre-charge pixel voltage is controlled and discharged by controlling the resistor and transistors, so that the desired grey scale is generated. The pixel circuit includes: a first switch, a second switch, a third switch, an energy storage device and resistor. By controlling the third switch, the first end of the energy storage device is charged to the voltage of the second source. The first switch and the second switch are controlled to switch on, so that the first end of the energy storage device discharging to the first source. The second switch switches off when the first end of the energy storage device reaches the desired pixel voltage.Type: GrantFiled: April 30, 2014Date of Patent: May 17, 2016Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Ya-Hsiang Tai, Lu-Sheng Chou, Chun-Yu Lin, Chia-Hung Chang
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Patent number: 9165960Abstract: A pixel circuit, an active sensing array, a sensing device, and a driving method thereof are provided. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and a data line. The reset transistor is electrically connected to a first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and a second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.Type: GrantFiled: June 10, 2013Date of Patent: October 20, 2015Assignee: Industrial Technology Research InstituteInventors: Ya-Hsiang Tai, Bo-Cheng Chen, Lu-Sheng Chou, Bo-Wen Xiao, Heng-Yin Chen
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Publication number: 20150077010Abstract: Provided is the pixel circuit for active matrix display apparatus and the driving method thereof, which is controlled by digital signal. The pre-charge pixel voltage is controlled and discharged by controlling the resistor and transistors, so that the desired grey scale is generated. The pixel circuit includes: a first switch, a second switch, a third switch, an energy storage device and resistor. By controlling the third switch, the first end of the energy storage device is charged to the voltage of the second source. The first switch and the second switch are controlled to switch on, so that the first end of the energy storage device discharging to the first source. The second switch switches off when the first end of the energy storage device reaches the desired pixel voltage.Type: ApplicationFiled: April 30, 2014Publication date: March 19, 2015Applicant: National Chiao Tung UniversityInventors: Ya-Hsiang TAI, Lu-Sheng CHOU, Chun-Yu LIN, Chia-Hung CHANG
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Publication number: 20140192035Abstract: A pixel circuit, an active sensing array, a sensing device, and a driving method thereof are provided. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and a data line. The reset transistor is electrically connected to a first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and a second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.Type: ApplicationFiled: June 10, 2013Publication date: July 10, 2014Inventors: Ya-Hsiang Tai, Bo-Cheng Chen, Lu-Sheng Chou, Bo-Wen Xiao, Heng-Yin Chen
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Patent number: 8723835Abstract: The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad.Type: GrantFiled: November 30, 2010Date of Patent: May 13, 2014Assignee: Au Optronics CorporationInventors: Hao-Lin Chiu, Chun-Yao Huang, Yih-Chyun Kao, Ya-Hsiang Tai, Lu-Sheng Chou, Kuan-Da Lin
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Patent number: 8546764Abstract: The present invention provides an active X-ray sensing circuit and the sensing method thereof, it is applied in X-ray panel. The X-ray sensing circuit comprises two row of pixel circuit, and the two row of pixel circuit shares one scan line, and each data line connects with two switches. It is compensated the threshold voltage when it switches to the current source. It operates reading when it switches to amplifier. By applying specific scan line signal, the last-row pixel circuit is compensated and the next-row pixel row is read at the same time, so that the sensing circuit array can compensate and sense in one scan to avoid the effect of the leakage current.Type: GrantFiled: August 28, 2012Date of Patent: October 1, 2013Assignee: National Chiao Tung UniversityInventors: Ya-Hsiang Tai, Lu-Sheng Chou, Bo-Cheng Chen
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Publication number: 20120287075Abstract: The invention discloses an active matrix touch sensing circuit apparatus used in a touch panel comprises a sensing unit, a resistance, and a thin film transistor. The resistance connects the sensing unit and the first scan line. The control end of the thin film transistor connects the sensing unit, the second scan line connects the input end of the thin film transistor, and the read out line connects the output end of the thin film transistor. When the sensing value of the body touch sensing unit is changed, and then the input wave form of the control end is changed. The output end generates an open current, and the read out line transmits the open current.Type: ApplicationFiled: June 29, 2011Publication date: November 15, 2012Applicant: National Chiao Tung UniversityInventors: Ya-Hsiang Tai, Lu-Sheng Chou, Hao-Lin Chiu
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Publication number: 20120133607Abstract: The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Hao-Lin Chiu, Chun-Yao Huang, Yih-Chyun Kao, Ya-Hsiang Tai, Lu-Sheng Chou, Kuan-Da Lin