Abstract: An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.

Abstract: An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.

Abstract: In a method and system for the automated construction and manipulation of a physical integrated circuit layout of a multiple-gate semiconductor device, wherein the layout is comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, working shapes of the gate glue-blocks are initially created according to user-defined gate glue-block parameters. Thereafter, working shapes of the active-layer glue-blocks are created in accordance with the working shapes of adjacent ones of the gate glue-blocks, in which the distances among the working shapes exceed minimum geometrical distances as defined by relevant design rules of an applied fabrication technology.