Patents by Inventor Lu Xiao

Lu Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200185270
    Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.
    Type: Application
    Filed: March 13, 2019
    Publication date: June 11, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Sha Sha Liu, EnBo Wang, Feng Lu, Li Hong Xiao, Haohao Yang, Zhaosong Li
  • Patent number: 10680003
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 10679985
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.
    Type: Grant
    Filed: November 17, 2018
    Date of Patent: June 9, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shasha Liu, Li Hong Xiao, EnBo Wang, Feng Lu, Qianbin Xu
  • Patent number: 10672711
    Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 2, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 10665500
    Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: May 26, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Sha Sha Liu, EnBo Wang, Feng Lu, Li Hong Xiao, Haohao Yang, Zhaosong Li
  • Patent number: 10662174
    Abstract: Provided are a series of BTK inhibitors, and specifically disclosed are a compound, pharmaceutically acceptable salt thereof, tautomer thereof or prodrug thereof represented by formula (I), (II), (III) or (IV).
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 26, 2020
    Assignee: HUBEI BIO-PHARMACEUTICAL INDUSTRIAL TECHNOLOGICAL INSTITUTE, INC.
    Inventors: Xuehai Wang, Chengde Wu, Yong Xu, Chunli Shen, Li'e Li, Guoping Hu, Yang Yue, Jian Li, Diliang Guo, Nengyang Shi, Lu Huang, Shuhui Chen, Ronghua Tu, Zhongwen Yang, Xuwen Zhang, Qiang Xiao, Hua Tian, Yanping Yu, Hailiang Chen, Wenjie Sun, Zhenyu He, Jie Shen, Jing Yang, Jing Tang, Wen Zhou, Jing Yu, Yi Zhang, Quan Liu
  • Publication number: 20200161618
    Abstract: Described herein, are battery separators, comprising the following: a microporous polymeric film; and an optional coating layer on at least one side of the microporous polymeric film, wherein at least one of the microporous polymeric film and the optional coating comprises an additive. The additive is selected from the group consisting of a lubricating agent, a plasticizing agent, a nucleating agent, a shrinkage reducing agent, a surfactant, an SEI improving agent, a cathode protection agent, a flame retardant additive, LiPF6 salt stabilizer, an overcharge protector, an aluminum corrosion inhibitor, a lithium deposition agent or improver, or a solvation enhancer, an aluminum corrosion inhibitor, a wetting agent, and a viscosity improver. Also, described herein are batteries, including lithium-ion batteries, comprising one or more of the described separators. Methods for making the battery separators are also described.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 21, 2020
    Inventors: Changqing Wang Adams, Kang Karen Xiao, Stefan Reinartz, Masaaki Okada, Brian R. Stepp, Yao Lu, Eric Robert White, Katharine Chemelewski
  • Patent number: 10658379
    Abstract: A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a slit vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the slit; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Lan Yao
  • Patent number: 10658378
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Xiaowang Dai, Yu Ting Zhou, Zhao Hui Tang, Mei Lan Guo, ZhiWu Tang, Qinxiang Wei, Qianbing Xu, Sha Sha Liu, Jian Hua Sun, Enbo Wang
  • Publication number: 20200126974
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.
    Type: Application
    Filed: November 17, 2018
    Publication date: April 23, 2020
    Inventors: Shasha Liu, Li Hong Xiao, EnBo Wang, Feng Lu, Qianbin Xu
  • Publication number: 20200035699
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 30, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun LIU, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
  • Publication number: 20200028593
    Abstract: The disclosure relates to a method performed by an optical receiver, the method comprising receiving an optical communication signal comprised in a signal space, the signal comprising a set of received training symbols and a set of received payload symbols, determining a kernel operating in a feature space by using the set of training symbols and a reference set of training symbols indicative of an undistorted version of the training symbols, wherein determining a kernel further comprises determining at least an equalization mapping function ƒ configured to map received symbols to channel equalized symbols, and determining an error function (e) configured to generate a measure indicative of an error between symbols mapped by the equalization mapping function ƒ and an ideal equalization mapping function, performing nonlinear equalization of the payload symbols (C?1 to C?M) by performing linear equalization of the payload symbols (C?1 to C?M) in the feature space using the received training symbols (C1 to CN) a
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Jiajia CHEN, Lu ZHANG, Xiaodan Pang, Shilin Xiao
  • Patent number: 10515975
    Abstract: A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 24, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Jun Chen, Xiaowang Dai, Jin Lyu, Jifeng Zhu, Jin Wen Dong, Lan Yao
  • Publication number: 20190378849
    Abstract: A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.
    Type: Application
    Filed: July 26, 2018
    Publication date: December 12, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qian Tao, Yushi HU, Zhenyu Lu, Li Hong XIAO, Jun CHEN, Xiaowang DAI, Jin LYU, Jifeng ZHU, Jin Wen DONG, Lan YAO
  • Patent number: 10475546
    Abstract: The present disclosure relates to conductors comprising a conducting member comprising silver and a functionalized organosiloxane network having at least one functional group capable of trapping silver or a silver ion as well as to methods of preparing the same. For example, the functionalized organosiloxane network can at least substantially inhibit dendrite formation between a first conducting member and a second conducting member. For example, the conductors may be used in an electronic circuit such as a printed electronic circuit.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 12, 2019
    Assignee: National Research Council of Canada
    Inventors: Gaozhi George Xiao, Ye Tao, Zhiyi Zhang, Jianping Lu
  • Publication number: 20190341399
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 7, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qian TAO, Yushi HU, Zhenyu LU, Li Hong XIAO, Xiaowang DAI, Yu Ting ZHOU, Zhao Hui TANG, Mei Lan GUO, ZhiWu TANG, Qinxiang WEI, Qianbing XU, Sha Sha LIU, Jian Hua SUN, Enbo WANG
  • Patent number: 10460219
    Abstract: In an example, a method is described that includes dividing an input image into a plurality of strips, where each strip is smaller than a whole of the input image. A plurality of binary images is then generated, where each of the binary images corresponds to one of the strips. Connected component labeling is performed on the binary images, one binary image at a time. An object map for the input image is then generated based on the results of the connected component labeling.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 29, 2019
    Assignees: Hewlett-Packard Development Company, L.P., Purdue Research Foundation
    Inventors: Brent Michael Bradburn, Zuguang Xiao, Mengqi Gao, Lu Wang, Jan P. Allebach
  • Publication number: 20190326314
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Application
    Filed: July 26, 2018
    Publication date: October 24, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong XIAO, Zhenyu LU, Qian TAO, Yushi HU, Jun CHEN, LongDong LIU, Meng WANG
  • Publication number: 20190326308
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Application
    Filed: July 26, 2018
    Publication date: October 24, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang PU, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Patent number: 10367637
    Abstract: A method of implementing security in a modular exponentiation function for cryptographic operations is provided. A key is obtained as a parameter when the modular exponentiation function is invoked. The key may be one of either a public key or a private key of a cryptographic key pair. Within the modular exponentiation function, the method ascertains whether the key is greater than L bits long, where L is a positive integer. A countermeasure against an attack is implemented if the key is greater than L bits long. The countermeasure may include one or more techniques (e.g., hardware and/or software techniques) that inhibit or prevent information about the key from being ascertained through analysis. One or more exponentiation operations may then be performed using the key. The same modular exponentiation function may be used to perform encryption and decryption operations but with different keys.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lu Xiao, Jing Deng, Justin Yongjin Kim