Patents by Inventor Lu-Yi Chen

Lu-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11101235
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 10950507
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 10796970
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Publication number: 20200152591
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventor: Lu-Yi Chen
  • Patent number: 10622323
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: April 14, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 10461002
    Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
  • Patent number: 10403570
    Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
  • Patent number: 10242972
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 26, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen, Guang-Hwa Ma, Cheng-Hsu Hsiao
  • Publication number: 20190057911
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Patent number: 10211082
    Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: February 19, 2019
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Publication number: 20190043798
    Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 7, 2019
    Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
  • Patent number: 10201086
    Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Cheng-Hsiang Liu, Chang-Lun Lu, Jun-Cheng Liao, Cheng-Yi Chen
  • Patent number: 10141233
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Patent number: 10128178
    Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
  • Publication number: 20180261563
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Inventor: Lu-Yi Chen
  • Publication number: 20180254227
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 6, 2018
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 9997481
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 12, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 9991178
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 5, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20180047610
    Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.
    Type: Application
    Filed: October 11, 2017
    Publication date: February 15, 2018
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Publication number: 20180042112
    Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 8, 2018
    Inventors: Lu-Yi Chen, Cheng-Hsiang Liu, Chang-Lun Lu, Jun-Cheng Liao, Cheng-Yi Chen