Patents by Inventor Lu Yuan

Lu Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8254279
    Abstract: Techniques for estimating thermal noise and rise-over-thermal (RoT) in a communication system are described. In an aspect, thermal noise in a sideband may be measured and used to estimate thermal noise in a signal band. In one design, received power in the sideband may be measured, e.g., by computing total power of FFT transform coefficients within the sideband. Thermal noise may be estimated based on (e.g., by filtering) the measured received power in the sideband. Received power in the signal band may also be measured. Total received power may be estimated based on (e.g., by filtering) the measured received power in the signal band. RoT may then be estimated based on the estimated thermal noise and the estimated total received power. The estimated RoT may be used to estimate an available load for a cell, which may be used to admit and/or schedule users in the cell.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: August 28, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Charles E. Wheatley, III, Avneesh Agrawal, Danlu Zhang, Sharad Deepak Sambhwani, Lu Yuan, Mehraban Iraninejad
  • Patent number: 8060929
    Abstract: There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: November 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Lu Yuan, Terence Chiu, Bolanle Oladapo Onodipe
  • Publication number: 20110102949
    Abstract: A method of fabricating a tunneling magnetoresistance (TMR) reader is disclosed. A TMR structure comprising at least one ferromagnetic layer and at least one nonmagnetic insulating layer is provided. A first thermal annealing process on the TMR structure is performed. A reader pattern definition process performed on the TMR structure to obtain a patterned TMR reader. A second thermal annealing process is performed on the patterned TMR reader.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: WESTERN DIGITAL (FREMONT), LLC
    Inventors: LU YUAN, JIAN X. SHEN, GEOFFREY W. ANDERSON, CHRISTOPHER NG
  • Publication number: 20110064301
    Abstract: Techniques and systems for providing textual attribute-based image categorization and search are disclosed herein. In some aspects, images may be analyzed to identify a category of an image, or portion thereof. Additional textual attributes may be identified and associated with the image. In various aspects, the categories may be types of sky sceneries. Categorized images may be searched based on the categories and/or attributes. In further aspects, a user interface may provide an intuitive arrangement of the images for user navigation and selection. The user interface may also provide a simplified presentation and search of the categorized images. Images selected from user interface may be used to replace or modify features of an existing target image.
    Type: Application
    Filed: September 16, 2009
    Publication date: March 17, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Jian Sun, Litian Tao, Lu Yuan
  • Publication number: 20100074552
    Abstract: Embodiments related to the removal of blur from an image are disclosed. One disclosed embodiment provides a method of performing an iterative non-blind deconvolution of a blurred image to form an updated image. The method comprises downsampling the blurred image to form a blurred image pyramid comprising images of two or more different resolution scales, downsampling a blur kernel to form a blur kernel pyramid comprising kernels of two or more different sizes, and deconvoluting a selected image in the blurred image pyramid according to a Richardson-Lucy deconvolution process in which a bilateral range/spatial filter is employed.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 25, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Jian Sun, Heung-Yeung Shum, Lu Yuan, Long Quan
  • Publication number: 20100048423
    Abstract: A simultaneous detection, differentiation and typing system of Newcastle disease and avian influenza viruses is provided. The present invention provides a system, including an oligonucleotide microarray, avian virus specific probes is disposed on the oligonucleotide microarray and the avian viruses include Newcastle disease and avian influenza viruses, and avian virus nucleic acid products, hybridized with the avian virus specific probes on the oligonucleotide microarray. The present invention describes a fast, simultaneous and inexpensive approach to the detection of Newcastle disease virus (NDV) and avian influenza virus (AIV) and possesses good sensitivity and specificity among divergent viruses. The hybridization results on microarrays were clearly identified with the naked eyes, with no further imaging equipment needed. The present invention provides potential for rapid surveillance and differential diagnosis of these two important zoonoses in both wild and domestic birds.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 25, 2010
    Applicant: ANIMAL HEALTH RESEARCH INSTITUTE, COUNCIL OF AGRICULTURE, EXECUTIVE YUAN
    Inventors: Chu-Hsiang Pan, Lih-Chiann Wang, Ching-Ho Wang, Ming-Chu Cheng, Ming-Hwa Jong, Shu-Hwae Lee, Lu-Yuan Liu
  • Publication number: 20100011160
    Abstract: There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.
    Type: Application
    Filed: September 21, 2009
    Publication date: January 14, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hugo Cheung, Lu Yuan, Terence Chiu, Bolanle Oladapo Onodipe
  • Publication number: 20090245212
    Abstract: Techniques for reporting acknowledgement (ACK) information and channel quality indication (CQI) information in a wireless communication system are described. A user equipment (UE) may be able to receive data from up to two cells with dual-cell operation. The UE may determine CQI information for a first cell, determine CQI information for a second cell, and send the CQI information for both cells on a feedback channel with a single channelization code. The UE may process a control channel from each cell and, if control information is received from the cell, may further process a data channel from the cell to receive data sent to the UE. The UE may determine ACK information for each cell based on processing results for the data and control channels from that cell. The UE may send the ACK information for both cells on the feedback channel with the single channelization code.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Sharad Deepak Sambhwani, Wei Zeng, Yibo Jiang, Lu Yuan, Mehmet Yavuz, Pavan Kumar Vitthaladevuni, Bibhu P. Mohanty, Danlu Zhang, Aziz Gholmieh, Arjun Bharadwaj
  • Publication number: 20090207746
    Abstract: Techniques for estimating thermal noise and rise-over-thermal (RoT) in a communication system are described. Thermal noise in a sideband may be measured and used as an estimate of thermal noise in a signal band. In one design, samples containing a desired signal centered at DC or a frequency higher than DC may be partitioned into blocks of K samples. Each block of K samples may be transformed with an FFT to obtain a corresponding block of K transform coefficients for K frequency bins. The power of transform coefficients for frequency bins in the sideband may be computed. Thermal noise may be estimated based on power values for the frequency bins in the sideband. Power values for frequency bins in the signal band may also be obtained and used to estimate total received power. RoT may then be estimated based on the estimated thermal noise and the estimated total received power.
    Type: Application
    Filed: September 30, 2008
    Publication date: August 20, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Lu Yuan, Danlu Zhang, Mehraban Iraninejad, Sharad Sambhwani
  • Publication number: 20090024776
    Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.
    Type: Application
    Filed: September 30, 2008
    Publication date: January 22, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hugo Cheung, Lu Yuan, Ramesh Saripalli
  • Publication number: 20080267086
    Abstract: Techniques for estimating thermal noise and rise-over-thermal (RoT) in a communication system are described. In an aspect, thermal noise in a sideband may be measured and used to estimate thermal noise in a signal band. In one design, received power in the sideband may be measured, e.g., by computing total power of FFT transform coefficients within the sideband. Thermal noise may be estimated based on (e.g., by filtering) the measured received power in the sideband. Received power in the signal band may also be measured. Total received power may be estimated based on (e.g., by filtering) the measured received power in the signal band. RoT may then be estimated based on the estimated thermal noise and the estimated total received power. The estimated RoT may be used to estimate an available load for a cell, which may be used to admit and/or schedule users in the cell.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 30, 2008
    Applicant: QUALCOMM Incorporated
    Inventors: Charles E. Wheatley, Avneesh Agrawal, Danlu Zhang, Sharad Deepak Sambhwani, Lu Yuan, Mehraban Iraninejad
  • Patent number: 7444440
    Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Lu Yuan, Ramesh Saripalli
  • Patent number: 7065669
    Abstract: A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In accordance with an exemplary embodiment, a conditional SFR write strobe signal may be used to trigger the SFR registers. A clock tree distribution process may be used to achieve significantly higher system speed. When balancing the clock network of the system, the clock leaf of the flip-flop or other circuit element that generates the SFR write strobe signal may be “advanced” by connecting the circuit element directly to the clock root. In addition, the SFR write strobe signal distribution may be balanced as a separate clock tree with minimum insertion delay.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Lu Yuan, Terence Chiu
  • Patent number: 6970951
    Abstract: An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external interface data transfer speed and input/output power consumption. In particular, the configuration bit allows the microprocessor user to establish the computer port as a memory port, input/output port or the like. The configuration bit is provided to the computer port at system power up or reset. Moreover, the configuration bit may be stored in flash memory and provided to the microprocessor computer port or, in the alternative, the configuration bit may be provided to the computer port directly via the microprocessor bus interface.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: November 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Terence Chiu, Lu Yuan
  • Patent number: 6952750
    Abstract: The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: October 4, 2005
    Assignee: Texas Instruments Incoporated
    Inventors: Hugo Cheung, Lu Yuan, Terence Chiu
  • Publication number: 20050214305
    Abstract: The present invention relates to a vascular endothelial cell inhibitor, VEGI, capable of inhibiting angiogenesis in cellular models and tumourigenesis in animal models, and methods of use.
    Type: Application
    Filed: December 14, 2004
    Publication date: September 29, 2005
    Applicants: Human Genome Sciences, Inc., Georgetown University Medical Center
    Inventors: Lu-Yuan Li, Yifan Zhai, Guo-Liang Yu, Jian Ni, Marc Lippman, Craig Rosen
  • Publication number: 20050010703
    Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 13, 2005
    Inventors: Hugo Cheung, Lu Yuan, Ramesh Saripalli
  • Publication number: 20040098519
    Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 20, 2004
    Inventors: Hugo Cheung, Lu Yuan, Ramesh Saripalli
  • Patent number: 6715000
    Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Lu Yuan, Ramesh Saripalli
  • Patent number: 6657888
    Abstract: Disclosed are two terminal bistable memory cells having least two high-spin polarization magnetic material junctions which are separated from one another by electron trap site defect containing insulator. The two terminal bistable memory cells demonstrate stable, low current readable, hysteretic resistance states which are set by the flow of a relatively high, (eg. a milliamp or less), plus or minus polarity D.C. current therethrough, which resistance is monitored by lower magnitude A.C. or D.C. current flow therethrough. Preferred cells have at least one CrO2/Cr2O3/CrO2 sequence but typically have multiple CrO2/Cr2O3/CrO2 sequences in series.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: December 2, 2003
    Assignee: Board of Regents of the University of Nebraska
    Inventors: Bernard Doudin, Andrei Sokolov, Cheol-Soo Yang, Lu Yuan, Sy-Hwang Liou