Abstract: Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

Abstract: Systems or methods of the present disclosure may provide an integrated circuit system, including programmable logic fabric and transceiver circuitry coupled to the programmable logic fabric, wherein the transceiver circuitry includes a parser configurable to parse a packet to identify a number of headers, a number of header offsets, or both, an extractor configurable to extract a number of fields from the number of heads, the number of header offsets, or both, and a classifier configurable to classify the packet to a stream based on the number of fields.

Abstract: Systems or methods of the present disclosure may provide an integrated circuit system including programmable logic circuitry and a transceiver tile coupled to the programmable logic circuitry, the transceiver tile including a transceiver subsystem. The transceiver subsystem may be configurable to store a precision time protocol (PTP) packet, generate a first copy of the PTP packet with a first timestamp, a second copy of the PTP packet with a second timestamp, and a third copy of the PTP packet with a third timestamp, encrypt each of the first copy of the PTP packet, the second copy of the PTP packet, and the third copy of the PTP packet, and transmit either the first copy of the PTP packet, the second copy of the PTP packet, or the third copy of the PTP packet.

Abstract: Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

Abstract: First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit. Next, the packet may be sent to a first in first out (FIFO) memory. The packet may then be sent from the FIFO memory out the port exit.

Abstract: First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit. Next, the packet may be sent to a first in first out (FIFO) memory. The packet may then be sent from the FIFO memory out the port exit.