Patents by Inventor Luan Nguyen

Luan Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294399
    Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: May 6, 2025
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ray Luan Nguyen, Benjamin Tomas Reyes, Geoffrey Hatcher, Stephen Jantzi
  • Publication number: 20250105154
    Abstract: Disclosed is an interconnect structure including a substrate, a conductive layer on the substrate, and a passivation layer in contact with the conductive layer, where the passivation layer includes a first layer including boron nitride (h-BN) having a hexagonal crystal structure and a second layer including amorphous boron nitride (a-BN), and the first layer is in contact with the conductive layer the first layer.
    Type: Application
    Filed: September 27, 2024
    Publication date: March 27, 2025
    Inventors: Giyoung JO, Sangwon KIM, Jaewon KIM, Hyeon Jin SHIN, Van Luan NGUYEN, Chang Seok LEE
  • Patent number: 12191392
    Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: January 7, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Van Luan Nguyen, Minsu Seol, Eunkyu Lee, Junyoung Kwon, Hyeonjin Shin, Minseok Yoo
  • Patent number: 12141499
    Abstract: Embodiments disclosed herein include managing playback devices with limited capabilities and playback devices with advanced capabilities by way of a control device. In some embodiments, the control device may control a first playback device by way of a legacy control application including a first control interface comprising first playback controls operable to control the first playback device in performing a set of legacy playback functions. The mobile device may control a second playback device by way of a production control application including a second control interface comprising second playback controls operable to control the second playback device in performing a set of production playback functions.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: November 12, 2024
    Assignee: Sonos, Inc.
    Inventors: Allison Elliot, Zachary Kramer, Dmitri Siegel, Lindsay Whitworth, Wescott Fleming, Dane Estes, Luan Nguyen, Avram Goldyne
  • Patent number: 12130086
    Abstract: A thermal storage battery is described. The thermal storage battery includes a battery core including a battery core shell made of stainless steel and a thermal storage material mixture included in the battery core shell, the thermal storage material mixture including a mixture of sand and graphite; a plurality of heating elements placed in the battery core, in which each heating element is surrounded by a respective protective tube; a plurality of wall thermal insulation layers, a lid thermal insulation layer, and a bottom thermal insulation layer that enclose the battery core; and at least one heat extraction pipe configured to collect heat from the battery core. The battery core, the plurality of heating elements, the plurality of wall thermal insulation layers, the lid thermal insulation layer, the bottom thermal insulation layer, and the at least one heating collection pipe are encased in a steel outer frame.
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: October 29, 2024
    Assignee: Alterno Pte. Ltd.
    Inventors: Nam Quoc Nguyen, Hai Viet Ho, Hung Van Quach, Phong Tue Mai, Luan The Nguyen
  • Patent number: 12103850
    Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: October 1, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Van Luan Nguyen, Keunwook Shin, Hyeonjin Shin, Changhyun Kim, Changseok Lee, Yeonchoo Cho
  • Publication number: 20240243751
    Abstract: An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Benjamin Tomas Reyes, Gabriele Minoia, Ray Luan Nguyen
  • Publication number: 20240242965
    Abstract: Provided are an amorphous boron nitride film, and a semiconductor device, a field effect transistor and an image sensor which include the same, and a method of manufacturing the amorphous boron nitride film. The amorphous boron nitride film includes a carbon atom-doped amorphous boron nitride compound, wherein an sp2 BN bonding structure and an sp3 BN bonding structure are included in the boron nitride film, an sp2/sp3 conjugated —C?C—C?C— dopant structure being distributed in 60% or less of the entire amorphous film.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicants: Samsung Electronics Co., Ltd., UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Taejin CHOI, Minsu KIM, Hyeonsuk SHIN, Jaewon KIM, Taehoon KIM, Hyeonjin SHIN, Van Luan NGUYEN
  • Patent number: 12005108
    Abstract: The present invention provides a Lactococcus lactis subspecies lactis isolate WFLU-12 with the accession number o KCTC 13180BP, and a use thereof.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: June 11, 2024
    Assignee: PUKYONG NATIONAL UNIVERSITY INDUSTRY-UNIVERSITY COOPERATION FOUNDATION
    Inventors: Do-Hyung Kim, Thanh Luan Nguyen, Nam-Eun Kim
  • Patent number: 12009921
    Abstract: A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 11, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ray Luan Nguyen, Dawood Alam, Nong Fan, Geoffrey Hatcher, Morteza Azarmnia
  • Publication number: 20240162337
    Abstract: A semiconductor device including a two-dimensional material is provided. The semiconductor device may include a two-dimensional material layer having semiconductor properties, a self-assembled monolayer in which self-assembled molecules are packed side-by-side, the self-assembled monolayer being arranged on the two-dimensional material layer, and an oxide layer arranged on the self-assembled monolayer.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Van Luan NGUYEN, Hyeonjin SHIN, Minsu SEOL, Yunseong LEE
  • Publication number: 20240162928
    Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 16, 2024
    Inventors: Ray Luan Nguyen, Benjamin Tomas Reyes, Geoffrey Hatcher, Stephen Jantzi
  • Patent number: 11961898
    Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Van Luan Nguyen, Minsu Seol, Junyoung Kwon, Hyeonjin Shin, Minseok Yoo, Yeonchoo Cho
  • Patent number: 11901925
    Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 13, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ray Luan Nguyen, Benjamin Tomas Reyes, Geoffrey Hatcher, Stephen Jantzi
  • Publication number: 20240034636
    Abstract: An amorphous boron nitride compound may include a boron nitride compound, where the boron nitride compound may be amorphous and may be doped with carbon or hydrogen. In the boron nitride compound, a total content of the carbon or the hydrogen may be in a range of about 0.1 at % to about 35 at % of a total atomic content.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Applicants: Samsung Electronics Co., Ltd., FUNDACIO INSTITUT CATALA DE NANOCIENCIA I NANOTECNOLOGIA (ICN2)
    Inventors: Stephan ROCHE, Aleandro ANTIDORMI, Onurcan KAYA, Van Luan NGUYEN, Hyeonjin SHIN, Taejin CHOI, Jaewon KIM, Taehoon KIM
  • Publication number: 20230402987
    Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 14, 2023
    Inventors: Stephane DALLAIRE, Ray Luan NGUYEN, Geaffrey HATCHER
  • Patent number: 11836589
    Abstract: Systems and methods for optimizing trained ML hardware models by collecting machine learning (ML) training inputs and outputs; selecting a ML model architecture from ML model architectures; training the selected ML model architecture with the ML training inputs and outputs; selecting a hardware processor from hardware processors; and creating a trained ML hardware model by inputting the selected hardware processor with the trained ML model. ML test inputs and outputs, and types of test metrics are selected and used to test the trained ML hardware model to provide runtime test metrics data for ML output predictions made by the trained ML hardware model. The trained ML hardware model is optimized to become an optimized trained ML hardware model using the runtime test metrics by selecting a new selected ML model architecture, selecting a new selected hardware processor, or updating the trained ML model using the runtime metrics test data.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: December 5, 2023
    Assignee: Eta Compute, Inc.
    Inventors: Justin Ormont, Evan Petridis, Luan Nguyen, Jeremi Wojcicki
  • Patent number: 11750166
    Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 5, 2023
    Assignee: Marvell Asia Pte. Ltd.
    Inventors: Stephane Dallaire, Ray Luan Nguyen, Geoffrey Hatcher
  • Patent number: 11750207
    Abstract: A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: September 5, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Ray Luan Nguyen, Geoffrey Hatcher
  • Publication number: 20230235276
    Abstract: The present invention provides a Lactococcus lactis subspecies lactis isolate WFLU-12 with the accession number o KCTC 13180BP, and a use thereof.
    Type: Application
    Filed: December 13, 2021
    Publication date: July 27, 2023
    Inventors: Do-Hyung KIM, Thanh Luan NGUYEN, Nam-Eun KIM