Abstract: A displaying base plate and a fabricating method thereof. The displaying base plate includes a substrate, and a first flat layer on one side of the substrate; a first metal layer on one side of the first flat layer that is further away from the substrate; a second flat layer on sides of the first metal layer and the first flat layer that are further away from the substrate; and a second metal layer on one side of the second flat layer that is further away from the substrate; wherein the first metal layer includes a first metal trace, an orthographic projection of the second metal layer on the substrate and an orthographic projection of the first metal trace on the substrate have an overlapping part, and an orthographic projection of the second flat layer on the substrate covers the orthographic projection of the first metal trace on the substrate.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1?i?I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.

Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.

Abstract: A mass transfer method for micro light-emitting diodes (W) includes: picking up micro light-emitting diodes (W) on an element substrate (200) by using a transfer substrate (300), and transferring the micro light-emitting diodes (W) after pickup to an intermediate carrying substrate (400); and transferring micro light-emitting diodes (W), which are on the intermediate carrying substrate (400) and correspond to all sub-pixels (SPX) on a target substrate (100), into the sub-pixels (SPX) of the target substrate (100) at one time, such that all the sub-pixels (SPX) on the target substrate (100) receives the micro light-emitting diodes (W) at one time.

Abstract: Disclosed are a display panel and a display apparatus. The display panel includes an opposing substrate, an array substrate and a liquid crystal layer. The array substrate includes: a first base substrate; a color film layer, includes a black matrix and a plurality of color resistors, the black matrix includes a plurality of pixel openings and a plurality of first light transmitting holes, and color resistors is arranged one pixel opening correspondingly; and photosensitive sensors, arranged between the color film layer and the first base substrate, orthographic projections of the plurality of photosensitive sensors on the first base substrate are in an orthographic projection of the black matrix on the first base substrate, and the orthographic projection of each of the plurality of photosensitive sensors on the first base substrate covers an orthographic projection of at least one the plurality of first light transmitting holes on the first base substrate.

Abstract: The present disclosure provides a color filter substrate and a method for manufacturing the same, and a display device, and the color filter substrate includes a base substrate, a black matrix and a color filter layer located on the base substrate, a quantum dot layer located on a side of the color filter layer away from the base substrate, a barrier layer located on a side of the black matrix away from the base substrate, and a first inorganic layer, and the first inorganic layer at least includes: a first portion located between the color filter layer and the quantum dot layer; a second portion located on the base substrate and between the quantum dot layer and the barrier layer; and a third portion located on a side of the barrier layer away from the base substrate.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1?i?I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.

Abstract: A display base plate, a preparation method therefor and a display panel are provided in the present disclosure. The display panel can greatly improve resolution while ensuring low power consumption. The display base plate includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a storage capacitor, a polysilicon transistor and at least one oxide transistor. The storage capacitor includes a first electrode and a second electrode oppositely arranged, and first electrode is arranged at a side of the second electrode away from the substrate. The second electrode is arranged in the same layer as a gate electrode of the polysilicon transistor. The at least one oxide transistor is arranged on a side of the first electrode away from the substrate, and the first electrode at least partially overlaps with an active layer of the at least one oxide transistor in a direction perpendicular to the substrate.

Abstract: A shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1?i?I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.

Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.

Abstract: A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth terminals thereof electrically coupled to the first node, a cathode of a photodiode and the second node, respectively; a photosensitive control circuit with first, second and third terminals thereof electrically coupled to an anode of the photodiode, the first node and the second node, respectively; an output circuit with first and second terminals thereof electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a pixel circuit, and the pixel circuit includes a light-emitting element, a driving circuit and a capacitor circuit. The driving circuit is configured to drive the light-emitting element to emit light; a first terminal of the capacitor circuit is electrically connected to a control terminal of the driving circuit, and a second terminal of the capacitor circuit is electrically connected to a data writing-in node; the capacitor circuit includes at least two capacitors connected in parallel with each other.

Abstract: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.

Abstract: Embodiments of the present disclosure provide a flexible sensor, including a flexible substrate; a plurality of ultrasonic detectors, on the flexible substrate; and a plurality of detection circuits, respectively corresponding to the ultrasonic detectors; wherein each of the detection circuits is between the flexible substrate and the corresponding ultrasonic detector, and configured to drive the ultrasonic detector to emit an ultrasonic wave, and detect a detection signal output by the ultrasonic detector after receiving the ultrasonic wave; each of the ultrasonic detectors includes: a first electrode coupled to the corresponding detection circuit, a second electrode on a side of the first electrode away from the flexible substrate, and a piezoelectric induction layer between the first electrode and the second electrode; a plurality of holes are provided in a region other than a region where the detection circuits are located.

Abstract: The embodiments of the present application disclose a touch control display panel and a manufacturing method thereof, a touch control display screen and a spliced screen. The touch control display panel comprises: A substrate; A driving circuit layer, wherein the driving circuit layer comprises a driving line and a data line, a touch control row electrode and a touch control column electrode, the touch control row electrode is connected to at least one row auxiliary electrode via at least one first via hole, and each row of touch control row electrodes are connected to each other in series via the row auxiliary electrode; the touch control column electrode is connected to at least one column auxiliary electrode through at least one second via, and each column touch control column electrode is connected to each other in series through the column auxiliary electrode.

Abstract: The embodiments of the present application disclose a touch control display panel and a manufacturing method thereof, a touch control display screen and a spliced screen. The touch control display panel comprises: A substrate; A driving circuit layer, wherein the driving circuit layer comprises a driving line and a data line, a touch control row electrode and a touch control column electrode, the touch control row electrode is connected to at least one row auxiliary electrode via at least one first via hole, and each row of touch control row electrodes are connected to each other in series via the row auxiliary electrode; the touch control column electrode is connected to at least one column auxiliary electrode through at least one second via, and each column touch control column electrode is connected to each other in series through the column auxiliary electrode.

Abstract: A fixture, a tray and a sputtering system. The fixture is internally provided with a support structure and a clamping structure connected with each other, wherein the clamping structure is configured to clamp a to-be-sputtered substrate; an orthographic projection of the clamping structure on a plane where the support structure is located and the support structure share an superimposed area and are separate in non-superimposed areas; wherein the support structure located in the non-superimposed area and/or the clamping structure located in the non-superimposed area has a first hollowed structure. The fixture is internally provided with the first hollowed structure, such that a part of an area of the to-be-sputtered substrate covered by the fixture may be exposed via the first hollowed structure when the fixture holds the to-be-sputtered substrate, so as to reduce the area of the to-be-sputtered substrate covered by the fixture.

Abstract: A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth terminals thereof electrically coupled to the first node, a cathode of a photodiode and the second node, respectively; a photosensitive control circuit with first, second and third terminals thereof electrically coupled to an anode of the photodiode, the first node and the second node, respectively; an output circuit with first and second terminals thereof electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively.

Abstract: Disclosed are a photoelectric conversion circuit, a driving method, a photoelectric detection substrate, a photoelectric detection device, and a first reset circuit supplies a signal of initialization signal terminal to a gate of driving transistor in response to a signal of reset control signal terminal. A conduction control circuit conducts a photoelectric conversion device with driving transistor in response to a signal of scan signal terminal, a threshold compensation circuit conducts gate of the driving transistor and a second electrode of driving transistor in response to signal at the scan signal terminal to compensate for a threshold voltage of driving transistor. A read control circuit conducts a first power supply terminal with first and second electrodes of driving transistor with a read output terminal in response to a signal of read control signal terminal to output a threshold voltage compensated signal generated by driving transistor to the read output terminal.