Abstract: The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating (80) a first file (FCH1) for configuring the test environment, and a second phase of generating (81) a second file (FCH2) for configuring at least a part of the design under test, the delivery of the first configuration file to a first reconfigurable hardware part (BTR) forming a reconfigurable test bench so as to configure the test bench, and the delivery of the second configuration file to a second reconfigurable hardware part (EML) so as to configure an emulator of the design under test, the two hardware parts being distinct and mutually connected.

Abstract: The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating (80) a first file (FCH1) for configuring the test environment, and a second phase of generating (81) a second file (FCH2) for configuring at least a part of the design under test, the delivery of the first configuration file to a first reconfigurable hardware part (BTR) forming a reconfigurable test bench so as to configure the test bench, and the delivery of the second configuration file to a second reconfigurable hardware part (EML) so as to configure an emulator of the design under test, the two hardware parts being distinct and mutually connected.

Abstract: A computer system is programmed with logic for automatically removing timing hazards from a circuit design. More specifically, the computer system is programmed with logic for automatically detecting and resolving clock gating as well as clock division timing hazards from the circuit design. In one embodiment, the computer system is further programmed with logic for logically organize timing hazards into levels, after the clock gating timing hazards have been resolved, and then resolving clock division timing hazards recursively. In one adaptation, the computer system is a component of a hardware emulation system.

Abstract: A computer system is programmed with logic for automatically removing timing hazards from a circuit design. More specifically, the computer system is programmed with logic for automatically detecting and resolving clock gating as well as clock division timing hazards from the circuit design. In one embodiment, the computer system is further programmed with logic for logically organize timing hazards into levels, after the clock gating timing hazards have been resolved, and then resolving clock division timing hazards recursively. In one adaptation, the computer system is a component of a hardware emulation system.