Patents by Inventor Luc De Schepper

Luc De Schepper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6136619
    Abstract: A method for measuring resistance changes is described to study electromigration induced failures in conductive patterns. This method can provide a basis for lifetime predictions based on low value failure criteria, i.e. small resistance changes in the conductive patterns in a limited period of time. Two essentially identical so-called test and reference structures are placed close to each other on the same substrate and submitted to at least one sequence of a stress period and a measurement period. During a stress period, a DC current with a high current density is applied to the test structure thereby enhancing electromigration, while substantially simultaneous an AC current is applied to the reference structure leading to the same amount of power dissipation in said reference structure as the amount of power dissipation in said test structure, introduced by said DC stress current.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: October 24, 2000
    Assignee: Interuniversitair Micorelektronica Centrum (IMEC, vzw)
    Inventors: Ward De Ceuninck, Luc De Schepper, Jan Van Olmen, Alessandro Goldoni
  • Patent number: 5927853
    Abstract: A method for evaluating the thermal impedance of packaged semiconductor chips. A measuring apparatus includes a thermostatic bath filled with a dielectric liquid and a temperature sensor for measuring the temperature of the bath. The semiconductor chip is subjected to a calibration step followed by a thermal response measurement step. Increasing the power pulse length allows measurement of the steady-state junction-to-case thermal resistance. The measuring apparatus and method is further used for tracing in-situ degradation of packaged semiconductor chips due to power cycling.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: July 27, 1999
    Inventors: Filip Christiaens, Luc Tielemans, Luc De Schepper, Eric Beyne
  • Patent number: 5915838
    Abstract: An apparatus and method for measuring a parameter of a sample or component at a measurement temperature, wherein the parameter and the measurement temperature are measured at substantially the same time. A temperature coefficient of the sample or component is also established by using temperature fluctuations measured at or near the sample at the time at which the parameter is measured. The temperature coefficient is used to correct the measured parameter data and enhance its stability.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: June 29, 1999
    Assignees: IMEC vzw, Limburgs Universitaire Campus
    Inventors: Lambert Stals, Luc De Schepper, Jean Roggen, Ward De Ceuninck
  • Patent number: 5833365
    Abstract: An apparatus and method for measuring a parameter of a sample or component at a measurement temperature, wherein the parameter and the measurement temperature are measured at substantially the same time. A temperature coefficient of the sample or component is also established by using temperature fluctuations measured at or near the sample at the time at which the parameter is measured. The temperature coefficient is used to correct the measured parameter data and enhance its stability.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: November 10, 1998
    Assignees: Interuniversitair Micro-Electronika Centrum vzw, Limburgs Universitair Centrum
    Inventors: Lambert Stals, Luc De Schepper, Jean Roggen, Ward De Ceuninck
  • Patent number: 5795063
    Abstract: A system for evaluating the thermal impedance of packaged semiconductor chips. The measuring apparatus includes a thermostatic bath filled with a dielectric liquid and a temperature sensor for measuring the temperature of the bath. The semiconductor chip is subjected to a calibration step followed by a thermal response measurement step. Increasing the power pulse length allows measurement of the steady-state junction-to-case thermal resistance. The measuring apparatus and method is further used for tracing in-situ degradation of packaged semiconductor chips due to power cycling.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: August 18, 1998
    Assignee: Interuniversitair Micro-Elektronica Centrum VZW
    Inventors: Filip Christiaens, Luc Tielemans, Luc De Schepper, Eric Beyne