Abstract: A method includes: receiving an integrated circuit design including a plurality of circuit modules; partitioning the integrated circuit design into a plurality of partitions in accordance with the plurality of circuit modules; assigning the plurality of partitions of the integrated circuit design to corresponding portions of an emulation system; inserting, by a processor, a plurality of emulation communication circuit structures into the plurality of circuit modules of the integrated circuit design, the corresponding portions of the emulation system being configured to communicate via one or more emulation interconnects connected to the emulation communication circuit structures, the emulation communication circuit structures being represented at a representation level selected from a group comprising: a packet level; a transaction level; and a protocol level; and emulating operation of the integrated circuit design using the emulation system.

Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.

Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.

Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.