Patents by Inventor Luc Francois Vidal

Luc Francois Vidal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High speed, low hardware footprint waveform
    Patent number: 11775716
    Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: October 3, 2023
    Assignee: Synopsys, Inc.
    Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
  • High Speed, Low Hardware Footprint Waveform
    Publication number: 20210150110
    Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Inventors: Arturo SALZ, Ching-Ping Chou, Jean-Philippe Colrat, Sebastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
  • High speed, low hardware footprint waveform
    Patent number: 10949588
    Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 16, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc François Vidal, Arnold Mbotchak