Abstract: The present invention relates to the use of HTRA1 mRNA antagonists in the treatment of eye disorders, such as macular degeneration, and the use of an HTRA1 levels in the aqueous and vitreous humor as a diagnostic biomarker for the suitability of treatment of a subject with an HTRA1 mRNA antagonist.

Abstract: A lipid particle comprising an apolipoprotein, a phosphatidylcholine and a lipid, such as a phospholipid, fatty acid or steroid lipid. In one embodiment the lipid particle comprises only one apolipoprotein. In one embodiment the lipid particle is consisting of one apolipoprotein, a phospholipid, a lipid, and a detergent. In one embodiment the lipid is a second phosphatidylcholine, wherein the first phosphatidylcholine and the second phosphatidylcholine differ in one or two fatty acid residues or fatty acid residue derivatives which are esterified to the glycerol backbone of the phosphatidylcholine. In one embodiment the apolipoprotein is selected from an apolipoprotein that has the amino acid sequence selected from SEQ ID NO: 01, 02, 06, 66, and 67, or is a variant thereof that has at least 70% sequence identity with the selected sequence.

Abstract: A lipid particle comprising an apolipoprotein, a phosphatidylcholine and a lipid, such as a phospholipid, fatty acid or steroid lipid. In one embodiment the lipid particle comprises only one apolipoprotein. In one embodiment the lipid particle is consisting of one apolipoprotein, a phospholipid, a lipid, and a detergent. In one embodiment the lipid is a second phosphatidylcholine, wherein the first phosphatidylcholine and the second phosphatidylcholine differ in one or two fatty acid residues or fatty acid residue derivatives which are esterified to the glycerol backbone of the phosphatidylcholine. In one embodiment the apolipoprotein is selected from an apolipoprotein that has the amino acid sequence selected from SEQ ID NO: 01, 02, 06, 66, and 67, or is a variant thereof that has at least 70% sequence identity with the selected sequence.

Abstract: These objects are achieved by a method of acoustically inspecting a one-piece bladed wheel in which the wheel is driven in rotation; each blade of the wheel is subjected to mechanical excitation; its acoustic response is picked up and a corresponding electrical signal is generated; its frequency response is determined by computing a FFT; the electrical signal and the associated frequency response are stored; the characteristic frequencies of each blade of the wheel are identified; and a wheel is rejected or accepted depending on whether or not the frequency distribution obtained in this way matches a predetermined set of forbidden frequency distributions. Advantageously, an additional step is provided in which the defects of a blade are determined by comparing its frequency response with predetermined frequency responses that are characteristic of various types of defect.

Abstract: These objects are achieved by a method of acoustically inspecting a one-piece bladed wheel in which the wheel is driven in rotation; each blade of the wheel is subjected to mechanical excitation; its acoustic response is picked up and a corresponding electrical signal is generated; its frequency response is determined by computing a FFT; the electrical signal and the associated frequency response are stored; the characteristic frequencies of each blade of the wheel are identified; and a wheel is rejected or accepted depending on whether or not the frequency distribution obtained in this way matches a predetermined set of forbidden frequency distributions. Advantageously, an additional step is provided in which the defects of a blade are determined by comparing its frequency response with predetermined frequency responses that are characteristic of various types of defect.

Abstract: A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a loop circuit having an instruction counter which counts execution of the instructions in the loop sequence and produces an end-of-sequence signal upon each completion of the loop, a register which refreshes the program counter with the address of the first instruction in the loop in response to each end-of-sequence signal, and a loop counter which counts the number of completions of the loop and delivers a signal indicating the end of the loop portion of the entire program and enabling the program counter to continue on with the rest of the program. The delay in loop execution permits initializing of registers in the data processor so as to permit pipeline execution of the loop instruction.

Abstract: A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented.

Abstract: A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.