Abstract: Data may be communicated from a sender device to a receiver device over enabled or selected byte positions or other data bit groups of a data bus. The sender device may determine data values to be sent over the data bus and may determine which byte positions are enabled or selected and which are not selected. The sender device may also determine a code. The code may be a value that is not included in the data values to be sent over the data bus. The sender device may then send the selected data values in selected byte positions of the data bus and send the code in non-selected byte positions of the data bus. The sender device may also send the code to the receiver device separately from the data bit lanes of the data bus.

Abstract: Data may be communicated from a sender device to a receiver device over enabled or selected byte positions or other data bit groups of a data bus. The sender device may determine data values to be sent over the data bus and may determine which byte positions are enabled or selected and which are not selected. The sender device may also determine a code. The code may be a value that is not included in the data values to be sent over the data bus. The sender device may then send the selected data values in selected byte positions of the data bus and send the code in non-selected byte positions of the data bus. The sender device may also send the code to the receiver device separately from the data bit lanes of the data bus.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Abstract: A method and controller for sending data frames over a lossy bidirectional link between integrated circuit chips is disclosed. Upon transmission, frames are stored in a buffer. The detection of errors is indicated and triggers retransmission of the erroneously received frame, but acknowledgement of correctly received frames is not indicated. Instead, the sending controller assumes that frames were correctly received if no error indication is received after a period of time. The period of time is the maximum amount of time that would be taken for the sending controller to receive an error indication if the frame was received with an error. After said period of time, the sent frame is discarded from the buffer.

Abstract: A method and controller for sending data frames over a lossy bidirectional link between integrated circuit chips is disclosed. Upon transmission, frames are stored in a buffer. The detection of errors is indicated and triggers retransmission of the erroneously received frame, but acknowledgement of correctly received frames is not indicated. Instead, the sending controller assumes that frames were correctly received if no error indication is received after a period of time. The period of time is the maximum amount of time that would be taken for the sending controller to receive an error indication if the frame was received with an error. After said period of time, the sent frame is discarded from the buffer.

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract: The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs.

Abstract: The message switching system (51) comprises at least two inputs (52, 53, 54, 55) and at least one output (56), first arbitration means (62) dedicated to said output (56), and management means (64) designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system (51) and having sent requests for the assignment of said output (56), and designed to assign said output (56). Said management means (64) comprise storage means (70) designed to store said relative orders OR(i,j), initialization means (66) designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means (68) designed to update all of said relative orders when a new request arrives at said first arbitration means (62), or when said output is assigned to one of said inputs.

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract: The process relates to the design of a circuit for synchronizing data asynchronously exchanged between two synchronous blocks. The circuit comprises at least one critical flip-flop capable of generating a decision signal for receiving a new data value. The process furthermore comprises: a step (20) for measuring the gain of the combinational loop of the critical flip-flop generating the decision signal for receiving a new data value; a step (21) for estimating a metastability resolution time from the said gain and a predetermined statistical mean time between failures; and a step (22) for adding the said resolution time to the synthesis time parameter of the said critical flip-flop or flip-flops, the said time parameter comprising the propagation time of the active edge of the clock timing signal of the receiving block, from the input of the said signal to the output of a critical flip-flop.

Abstract: The message switching system (51) comprises at least two inputs (52, 53, 54, 55) and at least one output (56), first arbitration means (62) dedicated to said output (56), and management means (64) designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system (51) and having sent requests for the assignment of said output (56), and designed to assign said output (56). Said management means (64) comprise storage means (70) designed to store said relative orders OR(i,j), initialization means (66) designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means (68) designed to update all of said relative orders when a new request arrives at said first arbitration means (62), or when said output is assigned to one of said inputs.

Abstract: The system for on-circuit asynchronous communication, between synchronous subcircuits, includes a first synchronous subcircuit regulated by a first clock frequency, which sends requests to a second synchronous subcircut regulated by a second clock frequency. The first subcircuit transmits data to the second subcircuit through a first mesochronous unidirectional communication link, and the second subcircuit transmits availability tokens which report the availability of an additional elementary memory location in the queue situated at the extremity of the first mesochronous unidirectional communication link to the first subcircuit, via a second mesochronous unidirectional communication link. The first subcircuit comprises means of transmission for directly transmitting to the second subcircuit data of a size that is at most equal to the size corresponding to the elementary memory locations available in the queue.

Abstract: System of transmitting data in an electronic circuit, comprising a set of signal transmission lines disposed roughly parallel to each other, each transmission line comprising inverting and non-inverting signal regeneration elements. Said set of transmission lines comprises four subsets of lines, each of which comprises at least one transmission line provided with a periodic arrangement of said inverting and non-inverting regeneration elements. Said respective regeneration elements are disposed in planes roughly perpendicular to said transmission lines. Four consecutive transmission lines disposed on the same level respectively belong to a separate subset of said subsets, and are disposed in a constant order.

Abstract: Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.

Abstract: Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.

Abstract: A recursive type adder for calculating the sum of two operands. It is used to calculate the sum of two binary data numbers using adders in the form of integrated circuits, particularly for information processing systems wherein the adders constitute one of the fundamental operations of data processing. The invention is classified in the category of parallel-parallel type adders.