Abstract: An apparatus comprises: a prediction storage structure comprising a plurality of prediction state entries representing instances of predicted instruction behaviour; prediction training circuitry to perform a training operation to train the prediction state entries based on actual instruction behaviour; prediction circuitry to output at least one control signal for triggering a speculative operation based on the predicted instruction behaviour represented by a prediction state entry for which the training operation has provided sufficient confidence in the predicted instruction behaviour; an allocation filter comprising at least one allocation filter entry representing a failed predicted instruction behaviour for which the training operation failed to provide said sufficient confidence; and prediction allocation circuitry to prevent allocation of a new entry in the prediction storage structure for a failed predicted instruction behaviour represented by an allocation filter entry of the allocation filter.

Abstract: Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.

Abstract: Circuitry comprises memory circuitry providing a plurality of memory locations; location selection circuitry to select a set of one or more of the memory locations by which to access a data item according to a mapping relationship between an attribute of the data item and the set of one or more memory locations; the location selection circuitry being configured to initiate an allocation operation for a data item when that data item is to be newly stored by the memory circuitry and the selected set of one or more of the memory locations are already occupied by one or more other data items, the allocation operation comprising an operation to replace at least a subset of the one or more other data items from the set of one or more memory locations by the newly stored data item; and detector circuitry to detect a data access conflict in which a group of two or more data items having different respective attributes are mapped by the mapping relationship to the same set of one or more memory locations; the locat

Abstract: A decoding apparatus has fetch circuitry, decode circuitry, and a decoded instruction cache. The decoded instruction cache comprises a plurality of cache blocks, where each cache block is arranged to store up to P decoded instructions from at least one fetch granule allocated to that cache block. When the corresponding decoded instruction for a required instruction is already stored in the decoded instruction cache, the decoded instruction is output in the stream of decoded instructions. Allocation circuitry is arranged, when a cache block is already allocated for existing decoded instructions from a particular fetch granule, and then additional decoded instructions from that particular fetch granule are subsequently produced by the decode circuitry due to a different path being taken through the fetch granule, to update the already allocated cache block to provide both the existing decoded instructions and the additional decoded instructions.

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry to execute instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop minimum iteration prediction circuitry having one or more entries, where each entry is associated with a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. During a training phase for an entry, the loop minimum iteration prediction circuitry seeks to identify a minimum number of iterations of the loop. The loop minimum iteration prediction circuitry is then arranged, when the training phase has successfully identified a minimum number of iterations, to subsequently identify a branch outcome prediction for the associated loop controlling branch instruction for use during the minimum number of iterations.

Abstract: An apparatus and method are provided for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period. The apparatus has regularity detection circuitry for seeking to detect such a regularity, and a storage providing a storage entry having a count value field to store a count value and a confidence indication field to indicate a confidence in the regularity. The regularity detection circuitry is arranged to consider the multiple instances of the counting period in pairs, for one instance in a given pair of the pairs the regularity detection circuitry incrementing the count value following each occurrence of the event, and for the other instance in the given pair the regularity detection circuitry decrementing the count value following each occurrence of the event.

Abstract: An apparatus and method are provided for making predictions for branch instructions. The apparatus has a prediction queue for identifying instructions to be fetched for execution, and branch prediction circuitry for making predictions in respect of branch instructions, and for controlling which instructions are identified in the prediction queue in dependence on the predictions. During each prediction iteration, the branch prediction circuitry makes a prediction for a predict block comprising a sequence of M instructions. The branch prediction circuitry comprises a target prediction storage having a plurality of entries that are used to identify target addresses for branch instructions that are predicted as taken, the target prediction storage being arranged as an N-way set associative storage structure comprising a plurality of sets. Each predict block has an associated set within the target prediction storage.

Abstract: An apparatus and method are provided for making predictions for branch instructions. The apparatus has a prediction queue for identifying instructions to be fetched for execution, and branch prediction circuitry for making predictions in respect of branch instructions, and for controlling which instructions are identified in the prediction queue in dependence on the predictions. During each prediction iteration, the branch prediction circuitry makes a prediction for a predict block comprising a sequence of M instructions. The branch prediction circuitry comprises a target prediction storage having a plurality of entries that are used to identify target addresses for branch instructions that are predicted as taken, the target prediction storage being arranged as an N-way set associative storage structure comprising a plurality of sets. Each predict block has an associated set within the target prediction storage.

Abstract: An apparatus is provided to perform branch prediction in respect of a plurality of instructions divided into a plurality of blocks. Receiving circuitry receives references to at least two blocks in the plurality of blocks. Branch prediction circuitry performs at least two branch predictions at a time. The branch predictions are performed in respect of the at least two blocks and the at least two blocks are non-contiguous.

Abstract: Circuitry comprises memory circuitry providing a plurality of memory locations; location selection circuitry to select a set of one or more of the memory locations by which to access a data item according to a mapping relationship between an attribute of the data item and the set of one or more memory locations; the location selection circuitry being configured to initiate an allocation operation for a data item when that data item is to be newly stored by the memory circuitry and the selected set of one or more of the memory locations are already occupied by one or more other data items, the allocation operation comprising an operation to replace at least a subset of the one or more other data items from the set of one or more memory locations by the newly stored data item; and detector circuitry to detect a data access conflict in which a group of two or more data items having different respective attributes are mapped by the mapping relationship to the same set of one or more memory locations; the locat

Abstract: An apparatus and method are provided for decoding instructions. The apparatus has fetch circuitry for fetching instructions from memory, where each instruction is from a fetch granule comprising P instructions at sequential addresses in the memory. Decode circuitry is then used to decode fetched instructions in order to produce a stream of decoded instructions for execution by the execution circuitry, and a decoded instruction cache is provided to store decoded instructions produced by the decode circuitry. The decoded instruction cache comprises a plurality of cache lines, where each cache line is arranged to store decoded instructions from at least one fetch granule allocated to that cache block, for each fetch granule allocated to the cache block the cache block being able to store up to P decoded instructions from that fetch granule.

Abstract: Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.

Abstract: An apparatus comprises: a prediction storage structure comprising a plurality of prediction state entries representing instances of predicted instruction behaviour; prediction training circuitry to perform a training operation to train the prediction state entries based on actual instruction behaviour; prediction circuitry to output at least one control signal for triggering a speculative operation based on the predicted instruction behaviour represented by a prediction state entry for which the training operation has provided sufficient confidence in the predicted instruction behaviour; an allocation filter comprising at least one allocation filter entry representing a failed predicted instruction behaviour for which the training operation failed to provide said sufficient confidence; and prediction allocation circuitry to prevent allocation of a new entry in the prediction storage structure for a failed predicted instruction behaviour represented by an allocation filter entry of the allocation filter.

Abstract: An apparatus and method are provided for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period. The apparatus has regularity detection circuitry for seeking to detect such a regularity, and a storage providing a storage entry having a count value field to store a count value and a confidence indication field to indicate a confidence in the regularity. The regularity detection circuitry is arranged to consider the multiple instances of the counting period in pairs, for one instance in the pair the regularity detection circuitry incrementing the count value following each occurrence of the event, and for the other instance in the pair the regularity detection circuitry decrementing the count value following each occurrence of the event.

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry to execute instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop minimum iteration prediction circuitry having one or more entries, where each entry is associated with a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. During a training phase for an entry, the loop minimum iteration prediction circuitry seeks to identify a minimum number of iterations of the loop. The loop minimum iteration prediction circuitry is then arranged, when the training phase has successfully identified a minimum number of iterations, to subsequently identify a branch outcome prediction for the associated loop controlling branch instruction for use during the minimum number of iterations.

Abstract: Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch ins

Abstract: An apparatus is provided to perform branch prediction in respect of a plurality of instructions divided into a plurality of blocks. Receiving circuitry receives references to at least two blocks in the plurality of blocks. Branch prediction circuitry performs at least two branch predictions at a time. The branch predictions are performed in respect of the at least two blocks and the at least two blocks are non-contiguous.

Abstract: Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch ins

Abstract: A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.

Abstract: A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.