Patents by Inventor Luc Petit

Luc Petit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411271
    Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Luc PETIT, Jerome LOPEZ, Karine SAXOD
  • Patent number: 10186466
    Abstract: An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Publication number: 20180033710
    Abstract: An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 1, 2018
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Publication number: 20180021855
    Abstract: An additive-manufacturing facility and a method for managing a powder transported to and from additive-manufacturing machines of the facility are provided. According to the method, a volume of feedstock powder is stored, and the machines are automatically fed with powder from the volume of feedstock powder. For each machine, the powder fed to the machine undergoes at least one layering operation during an additive-manufacturing cycle, and excess powder in the layering operation is moved away and conveyed from the machine to the volume of feedstock powder. For each machine, recovered powder, which is derived from cleaning rough components produced by the machine, is reintroduced into the volume of feedstock powder. A same collection circuit is used to convey the excess powder and the recovered powder to the volume of feedstock powder.
    Type: Application
    Filed: February 15, 2016
    Publication date: January 25, 2018
    Inventors: CHRISTOPHE DE LAJUDIE, JEAN-LUC PETIT-JEAN, CHRISTIAN GEAY
  • Patent number: 9818664
    Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 14, 2017
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Publication number: 20170250119
    Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Application
    Filed: August 18, 2016
    Publication date: August 31, 2017
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Patent number: 9006904
    Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Dominique Marais, Jacques Chavade, RĂ©mi Brechignac, Eric Saugier, Romain Coffy, Luc Petit
  • Patent number: 6528407
    Abstract: Process for producing electrical-connections on a semiconductor package containing an integrated-circuit chip and with an external protective layer having apertures that least partly expose metal electrical-connection regions, and semiconductor package provided with such metal electrical-connections. The apertures having walls are filled with a metal electrical-connection layer covering at least their walls. A metal solder drop is soldered to the connection layer so that it is not in contact with the external protective layer.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: March 4, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Petit, Alexandre Castellane
  • Patent number: 6399475
    Abstract: Process for producing electrical connections on the surface of a semiconductor package containing an integrated-circuit chip and having metal electrical-connection regions on the surface of the package, consisting of: covering these connection regions with a first metal layer forming an anti-diffusion barrier; covering this first layer with an anti-oxidation second metal layer; and depositing a metal solder drop or solder ball on the second metal layer. The solder drop comprises an addition of metal particles in suspension which contain at least one of the metals of the first metal layer so as to produce a precipitate comprising these additional metal particles and at least partly the metal of the second metal layer, the precipitate remaining in suspension in the solder drop.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: June 4, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Luc Petit
  • Patent number: 6049971
    Abstract: A method for fabricating a lead frame that includes a platform attached thereto for mounting a chip. A base frame is provided for mounting chips of various sizes. The base frame includes connection leads extending toward a central portion, which is substantially of the size of the smallest chip to mount. Connection leads are cut-out about the central portion to form an opening corresponding to the size of the chip to be mounted. A platform is soldered to at least two support leads to form the lead frame.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 18, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Luc Petit
  • Patent number: 5959355
    Abstract: A semiconductor package having an array of solder pads and supportive elements that are mechanically and electrically bonded to the solder pads and that do not collapse during the bonding process, wherein the supportive elements are annular.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 28, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Luc Petit