Abstract: A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved.

Abstract: In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. The processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. The processor capacity monitor calculate a percentage usage of a total capacity of the physical processors from the logical usage percentages and the physical usage percentages, such that the percentage usage reflects the actual use of the physical processors independent of which of the threads is used.

Abstract: A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved.

Abstract: In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a method, system, and program for monitoring the percentage usage of the total capacity of the physical processors is provided. A processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. In addition, the processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. Then, the processor capacity monitor multiplies the logical usage percentage and physical usage percentage for each of the threads and sums the result. The summed result is divided by the number of physical processors to determine the percentage usage of the total capacity of the physical processors.

Abstract: A power level monitor and performance tracking tool are provided for correlating system performance with processor management events. When power management requires a change to the state of a microprocessor, software will be notified. Multiple layers of software may be notified, including a firmware level, an operating system, as well as applications. The performance tracking tool tracks the times of the power management events as well as their impact to the microprocessor performance. The performance tracking tool may then display or record the state changes to processor performance. These changes may be correlated against other system events to aid in determining system performance problems with respect to power management.

Abstract: In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a method, system, and program for monitoring the percentage usage of the total capacity of the physical processors is provided. A processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. In addition, the processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. Then, the processor capacity monitor multiplies the logical usage percentage and physical usage percentage for each of the threads and sums the result. The summed result is divided by the number of physical processors to determine the percentage usage of the total capacity of the physical processors.

Abstract: A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, remains consistent despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent way to update performance counts.

Abstract: A method and system within a symmetrical multi-processing system or information handling system are disclosed for compensating all the processor clocks when performing instruction level tracing. The method provides a simple and flexible mechanism to slow down the clock proportionally to the density of the trace. According to the present invention, the method determines two parameters; a trigger and a compensation step. The trigger is defined as the number of instructions between clock increments and the compensation step is the number of ticks to add to a clock. When the trigger is equal to one, the clock is incremented at each tracing step by an amount equal to the compensation step multiplied by the number of instructions since the last compensation. When the trigger is greater than one, the compensation step is equal to one and the clock is incremented by one every time the number of instructions since the last compensation is bigger than the trigger.

Abstract: A method and system within a data processing system or information handling system are disclosed for counting various events from a running program (hereafter called a process) by taking a trace by way of using an interruption. According to the present invention, a performance monitor feature within a data processing system is programmed to generate a trace interrupt after each branch instruction, or at the end of each basic block of code from a currently running program or process. By programming monitor mode control registers within the performance monitor feature, one or more counters are programmed to count various events happening on the data processing system thereby creating tracing information. If the current process is a process to be traced, the tracing information is stored in a trace buffer for post-processing analysis, the counters are reset to zero returning back to the process from the interrupt.

Abstract: A method and system within a data processing system are disclosed for directly accessing code during a process by taking a trace by way of using an interruption. According to the present invention, the processor is programmed to generate a trace interrupt after each branch, or at the end of each basic block from the current process. This allows generation of exactly the same number of interruptions as would be produced by an instrumentation approach but without having to know where the basic blocks are in advance. By programming the performance monitor feature to count instructions, the exact size of each basic block is known. At each interrupt, the address of the beginning of the next basic block is saved which is the address where the interruption came from. Tracing information for the previous basic block including its address and its size (the current value of a counter) is created.

Abstract: A process and apparatus for writing an item of data to a line in a memory table shared by a plurality of processors is disclosed. The process comprises the steps of determining if the item is already in the line; if the item is not in the line, then determining if the line is empty; if the line is empty, then performing the following steps: creating a reservation for the line for a processor requesting to write the item to the line and trying to write, by the processor requesting to write the item to the line, the item to the line. Although more than one processor can hold a reservation for the line, only one processor can add an item to the line since the reservation for the line is removed or cleared in all processors when the first processor, holding a reservation for the line, writes an item to the line.