Abstract: A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

Abstract: A netlist is updated based on an engineering change order (ECO) circuit network by determining primary cuts of a first network of a netlist and secondary cuts of the ECO circuit network. The primary cuts are at least a portion of the first network, and include one or more logic elements and an output node. The secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements and an output node. Further, matching cuts are determined from the primary cuts and the secondary cuts. The matching cuts include a first cut of the primary cuts and a second cut of the secondary cuts. A downward frontier of the ECO circuit network is determined from the matching cuts, and the netlist is updated based on the downward frontier.