Abstract: A power semiconductor device comprises a semiconductor body, a gate electrode, and an extraction electrode, wherein the semiconductor body comprises a source region of a first conductivity type, a well region of a second conductivity type different from the first conductivity type at the gate electrode, a drift region which is of the first conductivity type, and a barrier region which is of the first conductivity type, the barrier region is located between the drift region and the extraction electrode.

Abstract: A power semiconductor device and method of manufacture thereof involving drift layer of a first conductivity type; base layer of a second conductivity type different than the first conductivity type; source region with first conductivity type arranged on a side of the base layer facing away from the drift layer; a first trench extending from the emitter side into the drift layer; an insulated trench gate electrode extending into the first trench; a second trench being arranged on a side of a first trench facing away from the source region; an electrically conductive layer extending into the second trench and electrically insulated from the base layer and the drift layer. A portion of the base layer extends from the emitter side at least as deep in the vertical direction towards the collector side as the at least one second trench.

Abstract: The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.