Abstract: A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

Abstract: A multiple output DC-DC converter comprises a transformer, a primary circuit, a plurality of secondary circuits, and a controller. The transformer has a primary and at least one secondary winding. The primary circuit connects to a DC power supply source and includes the primary winding of the transformer and a primary switch connected in series. The plurality of secondary circuits includes the at least one secondary winding of the transformer, wherein each secondary circuit provides a DC power supply output, and at least one of the secondary circuits has a secondary switch. The controller monitors an output signal of each secondary circuit and controls operation of the primary and secondary switches based on the monitored signals. The controller co-ordinates operation of the secondary switch with the primary switch, such that the primary switch and the secondary switch are switched on simultaneously, or with a controlled offset.

Abstract: A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract: A multiple output DC-DC converter comprises a transformer, a primary circuit, a plurality of secondary circuits, and a controller. The transformer has a primary and at least one secondary winding. The primary circuit connects to a DC power supply source and includes the primary winding of the transformer and a primary switch connected in series. The plurality of secondary circuits includes the at least one secondary winding of the transformer, wherein each secondary circuit provides a DC power supply output, and at least one of the secondary circuits has a secondary switch. The controller monitors an output signal of each secondary circuit and controls operation of the primary and secondary switches based on the monitored signals. The controller co-ordinates operation of the secondary switch with the primary switch, such that the primary switch and the secondary switch are switched on simultaneously, or with a controlled offset.

Abstract: A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.

Abstract: A configurable Turbo-LDPC decoder comprising: A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory.

Abstract: An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.

Abstract: Systems and methods for transferring a stream of at least one data packet between a first electronic device and second electronic device through a network-on-chip are disclosed. These systems and methods can comprise storing data packets in memory means provided in a network interface and transferring data packets from the memory means to the second electronic device. Packets can be transferred from the memory means after a quantity of packets is stored in the memory means, the quantity of packets being determined according to a value of a control parameter.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.

Abstract: A receiver for receiving digital signals exposed to intersymbol interference as well as multiple access interference the method including linearly detecting said signals by combating said intersymbol interference by equalizing said received digital signals as well as mitigating said multiple access interference by detecting said digital signals using sliding window detection.

Abstract: An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver loading.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver. loading.

Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.

Abstract: A receiver for receiving digital signals exposed to intersymbol interference as well as multiple access interference the method including linearly detecting said signals by combating said intersymbol interference by equalizing said received digital signals as well as mitigating said multiple access interference by detecting said digital signals by means of sliding window detection.

Abstract: An adaptive signal receiver comprising at least one blind detection unit arranged to be robust to asynchronous multiple access interference (MAI). The useful signal is detected using a user signature sequence comprised of a fixed term and a complex adaptive part having a length that extends over a number of samples within a defined observation window. Provision is made for updating automatically and periodically the complex adaptive part of the signature sequence.

Abstract: The invention relates to the recognition of a spread spectrum data signal transmitted in code division multiple access communication systems. The invention provides a receiver whose code acquisition and detection circuit includes circuitry configured for detecting the signal received by using an audio adaptive detection threshold generated locally from the output signal of the detection circuit itself. The invention is used for example, in terrestrial or satellite radio communication systems.